DE60232474D1 - Integrierter Halbleiterschaltkreis und zugehöriges Herstellungsverfahren - Google Patents

Integrierter Halbleiterschaltkreis und zugehöriges Herstellungsverfahren

Info

Publication number
DE60232474D1
DE60232474D1 DE60232474T DE60232474T DE60232474D1 DE 60232474 D1 DE60232474 D1 DE 60232474D1 DE 60232474 T DE60232474 T DE 60232474T DE 60232474 T DE60232474 T DE 60232474T DE 60232474 D1 DE60232474 D1 DE 60232474D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated semiconductor
associated manufacturing
manufacturing
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60232474T
Other languages
English (en)
Inventor
Akio Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Application granted granted Critical
Publication of DE60232474D1 publication Critical patent/DE60232474D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60232474T 2001-01-23 2002-01-16 Integrierter Halbleiterschaltkreis und zugehöriges Herstellungsverfahren Expired - Lifetime DE60232474D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001015042A JP4765014B2 (ja) 2001-01-23 2001-01-23 半導体集積回路装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE60232474D1 true DE60232474D1 (de) 2009-07-16

Family

ID=18881658

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60232474T Expired - Lifetime DE60232474D1 (de) 2001-01-23 2002-01-16 Integrierter Halbleiterschaltkreis und zugehöriges Herstellungsverfahren

Country Status (4)

Country Link
US (2) US6833594B2 (de)
EP (1) EP1225626B1 (de)
JP (1) JP4765014B2 (de)
DE (1) DE60232474D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100582374B1 (ko) * 2004-09-08 2006-05-22 매그나칩 반도체 유한회사 고전압 트랜지스터 및 그 제조 방법
US9159568B2 (en) * 2006-02-04 2015-10-13 Cypress Semiconductor Corporation Method for fabricating memory cells having split charge storage nodes
US8866263B2 (en) * 2006-09-26 2014-10-21 Texas Instruments Incorporated Emitter ballasting by contact area segmentation in ESD bipolar based semiconductor component
JP5332781B2 (ja) * 2009-03-19 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
JP5330899B2 (ja) * 2009-05-25 2013-10-30 株式会社東芝 半導体装置及びその製造方法
JP2011096862A (ja) * 2009-10-30 2011-05-12 Hitachi Ltd 半導体装置及びその製造方法
JP5648413B2 (ja) * 2009-11-09 2015-01-07 東芝ライテック株式会社 照明装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
JPS6010780A (ja) 1983-06-30 1985-01-19 Fujitsu Ltd 半導体装置の製造方法
JPS60105277A (ja) 1983-11-11 1985-06-10 Toshiba Corp Ｍｏｓトランジスタの製造方法
JPS61190983A (ja) 1985-02-20 1986-08-25 Hitachi Ltd 半導体集積回路装置
JP2545762B2 (ja) * 1990-04-13 1996-10-23 日本電装株式会社 高耐圧ｍｉｓトランジスタおよびこのトランジスタを有する相補型トランジスタの製造方法
US5559044A (en) * 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
US5409848A (en) * 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
JP3055424B2 (ja) * 1994-04-28 2000-06-26 株式会社デンソー Ｍｉｓ型半導体装置の製造方法
JP3601612B2 (ja) * 1994-09-22 2004-12-15 富士通株式会社 半導体装置及びその製造方法
US5516711A (en) * 1994-12-16 1996-05-14 Mosel Vitelic, Inc. Method for forming LDD CMOS with oblique implantation
US6127700A (en) * 1995-09-12 2000-10-03 National Semiconductor Corporation Field-effect transistor having local threshold-adjust doping
JP3386101B2 (ja) * 1996-08-29 2003-03-17 シャープ株式会社 半導体装置の製造方法
US5830789A (en) * 1996-11-19 1998-11-03 Integrated Device Technology, Inc. CMOS process forming wells after gate formation
US5899732A (en) * 1997-04-11 1999-05-04 Advanced Micro Devices, Inc. Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device
US6096591A (en) * 1997-06-30 2000-08-01 Advanced Micro Devices, Inc. Method of making an IGFET and a protected resistor with reduced processing steps
US6294416B1 (en) * 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US5963799A (en) * 1998-03-23 1999-10-05 Texas Instruments - Acer Incorporated Blanket well counter doping process for high speed/low power MOSFETs
US6157062A (en) * 1998-04-13 2000-12-05 Texas Instruments Incorporated Integrating dual supply voltage by removing the drain extender implant from the high voltage device
JP3536693B2 (ja) * 1998-11-24 2004-06-14 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
US6238982B1 (en) * 1999-04-13 2001-05-29 Advanced Micro Devices Multiple threshold voltage semiconductor device fabrication technology
TW411509B (en) * 1999-06-05 2000-11-11 United Microelectronics Corp Integrated manufacturing method of high voltage and low voltage device
JP3546783B2 (ja) * 1999-06-09 2004-07-28 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
TW466704B (en) * 1999-09-10 2001-12-01 Koninkl Philips Electronics Nv Integrated circuit
US6355531B1 (en) * 2000-08-09 2002-03-12 International Business Machines Corporation Method for fabricating semiconductor devices with different properties using maskless process

Also Published As

Publication number Publication date
EP1225626A2 (de) 2002-07-24
JP2002222867A (ja) 2002-08-09
EP1225626B1 (de) 2009-06-03
EP1225626A3 (de) 2005-01-12
US20040232498A1 (en) 2004-11-25
US7138311B2 (en) 2006-11-21
US6833594B2 (en) 2004-12-21
JP4765014B2 (ja) 2011-09-07
US20020117723A1 (en) 2002-08-29

Similar Documents

Publication Publication Date Title
DE60019913D1 (de) Halbleiterbauelement und Herstellungsverfahren
DE60319898D1 (de) Halbleiter-Bauelement und Herstellungsverfahren
TWI348756B (en) A semiconductor integrated circuit device and a method of manufacturing the same
SG118117A1 (en) Semiconductor device and manufacturing method thereof
DE60037057D1 (de) Halbleiterelement und Herstellungsverfahren dafür
DE60030931D1 (de) Halbleiteranordnung und Herstellungsverfahren dafür
DE602004009821D1 (de) Halbleiterbauelement und Herstellungsverfahren dafür
SG121710A1 (en) Semiconductor device and fabrication method thereof
SG121715A1 (en) Semiconductor device and method of manufacturing the same
DE60220762D1 (de) Halbleiterbauelement und zugehöriges Herstellungsverfahren
DE60230840D1 (de) Halbleiteranordnung und Herstellungsverfahren dafür
DE60135728D1 (de) Integrierte Halbleiterschaltung
GB2393325B (en) Semiconductor device and manufacturing method thereof
DE60210834D1 (de) Halbleiterbauelement und zugehöriges Herstellungsverfahren
GB2382923B (en) Semiconductor integrated circuit and its layout method
DE60231538D1 (de) Sputtertarget und herstellungsverfahren dafür
SG102653A1 (en) Semiconductor integrated circuit and fabrication process therefor
DE60134189D1 (de) Halbleiteranordnung und Herstellungsverfahren
EP1424409A4 (de) Halbleiterscheibe und verfahren zu ihrer herstellung
DE60322190D1 (de) Halbleiteranordnung und entsprechendes Herstellungsverfahren
GB0130018D0 (en) Semiconductor devices and their manufacture
DE60221625D1 (de) Integrierte Halbleiterschaltung
EP1363333A4 (de) Halbleiterbauelement und verfahren zu seiner herstellung
DE60302916D1 (de) Halbleiterlaser und Herstellungsverfahren
DE60227139D1 (de) Halbleiter-IC-Module, Herstellungsmethode und Verwendung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJI ELECTRIC SYSTEMS CO., LTD., TOKYO/TOKIO, JP