DE60220471D1 - Einrichtung und Verfahren zum Entwurf von logischen Schaltungen mit reduziertem Leckstrom - Google Patents

Einrichtung und Verfahren zum Entwurf von logischen Schaltungen mit reduziertem Leckstrom

Info

Publication number
DE60220471D1
DE60220471D1 DE60220471T DE60220471T DE60220471D1 DE 60220471 D1 DE60220471 D1 DE 60220471D1 DE 60220471 T DE60220471 T DE 60220471T DE 60220471 T DE60220471 T DE 60220471T DE 60220471 D1 DE60220471 D1 DE 60220471D1
Authority
DE
Germany
Prior art keywords
logic circuits
reduced leakage
leakage logic
designing
designing reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60220471T
Other languages
English (en)
Other versions
DE60220471T2 (de
Inventor
Kimiyoshi Usami
Naoyuki Kawabe
Takeshi Kitahara
Masahiro Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE60220471D1 publication Critical patent/DE60220471D1/de
Publication of DE60220471T2 publication Critical patent/DE60220471T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE60220471T 2001-04-02 2002-04-02 Einrichtung und Verfahren zum Entwurf von logischen Schaltungen mit reduziertem Leckstrom Expired - Lifetime DE60220471T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001103695 2001-04-02
JP2001103695A JP2002299454A (ja) 2001-04-02 2001-04-02 論理回路設計方法、論理回路設計装置及び論理回路マッピング方法

Publications (2)

Publication Number Publication Date
DE60220471D1 true DE60220471D1 (de) 2007-07-19
DE60220471T2 DE60220471T2 (de) 2008-02-07

Family

ID=18956712

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60220471T Expired - Lifetime DE60220471T2 (de) 2001-04-02 2002-04-02 Einrichtung und Verfahren zum Entwurf von logischen Schaltungen mit reduziertem Leckstrom

Country Status (4)

Country Link
US (1) US6813750B2 (de)
EP (1) EP1248370B1 (de)
JP (1) JP2002299454A (de)
DE (1) DE60220471T2 (de)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6711720B2 (en) * 2002-03-14 2004-03-23 Hewlett-Packard Development Company, L.P. Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization
US6745371B2 (en) * 2002-03-15 2004-06-01 Sun Microsystems, Inc. Low Vt transistor substitution in a semiconductor device
US7451413B1 (en) 2003-01-03 2008-11-11 Marvell International Ltd. Methods of minimizing leakage current by analyzing post layout information and associated threshold voltage and leakage current
US6910197B2 (en) * 2003-06-20 2005-06-21 Sun Microsystems, Inc. System for optimizing buffers in integrated circuit design timing fixes
US7084464B2 (en) * 2003-07-10 2006-08-01 Stmicroelectronics, Inc. Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same
US7032200B1 (en) 2003-09-09 2006-04-18 Sun Microsystems, Inc. Low threshold voltage transistor displacement in a semiconductor device
JP3990339B2 (ja) 2003-10-30 2007-10-10 株式会社東芝 回路自動設計装置、回路自動設計方法及び回路自動設計プログラム
US7100144B2 (en) * 2003-12-09 2006-08-29 International Business Machines Corporation System and method for topology selection to minimize leakage power during synthesis
JP4733999B2 (ja) * 2005-03-08 2011-07-27 富士通株式会社 回路設計方法、回路設計装置及び半導体回路
US7500207B2 (en) * 2006-02-15 2009-03-03 International Business Machines Corporation Influence-based circuit design
KR101048751B1 (ko) * 2006-06-30 2011-07-14 인텔 코포레이션 누설 전력 추정 장치, 방법 및 컴퓨팅 시스템
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8456193B2 (en) 2010-09-17 2013-06-04 Qualcomm Incorporated Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
KR101891373B1 (ko) 2011-08-05 2018-08-24 엠아이이 후지쯔 세미컨덕터 리미티드 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426591A (en) 1994-01-28 1995-06-20 Vlsi Technology, Inc. Apparatus and method for improving the timing performance of a circuit
US5774367A (en) 1995-07-24 1998-06-30 Motorola, Inc. Method of selecting device threshold voltages for high speed and low power
JP3777768B2 (ja) 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
JP3853576B2 (ja) 2000-06-29 2006-12-06 株式会社東芝 回路自動生成装置、回路自動生成方法及び回路自動生成プログラムを記載した記録媒体
JP2002215705A (ja) * 2001-01-23 2002-08-02 Toshiba Corp 回路自動生成装置、回路自動生成方法及び回路自動生成プログラムを記録した記録媒体

Also Published As

Publication number Publication date
DE60220471T2 (de) 2008-02-07
EP1248370B1 (de) 2007-06-06
US6813750B2 (en) 2004-11-02
EP1248370A1 (de) 2002-10-09
JP2002299454A (ja) 2002-10-11
US20020144223A1 (en) 2002-10-03

Similar Documents

Publication Publication Date Title
DE60220471D1 (de) Einrichtung und Verfahren zum Entwurf von logischen Schaltungen mit reduziertem Leckstrom
DE60329738D1 (de) Verfahren und System zum Drucken von integrierten Schaltungsplänen
DE50111563D1 (de) Inselnetz und verfahren zum betrieb eines inselnetzes
ATE454858T1 (de) Verfahren und gerät zum entwurf von orthodontischen vorrichtungen
DE60228160D1 (de) System und Verfahren zum Durchführen von drahtlosen Transaktionen
DE60138942D1 (de) Verfahren zum Weiterreichen und Agentvorrichtung
DE10293613D2 (de) Getriebe und Verfahren zum Druchführen von Schaltvorgängen
DE60318069D1 (de) Schaltung und verfahren zum prüfen eingebetteter dram-schaltungen durch direktzugriffsmodus
DE50305694D1 (de) Elektromagnetische reibschlüssige schaltkupplung und verfahren zu ihrem betrieb
DE19882461T1 (de) Verfahren und Schaltung zum Betrieb eines Transistors als Gleichrichter
DE60136763D1 (de) Metallisierungsgerät und Verfahren zur Entfernung von Metallisierungsflüssigkeit
DE60129793D1 (de) Verfahren zum transfer und stapeln von halbleiterbausteinen
DE69931685D1 (de) Verfahren und Gerät zum Implementieren von schnellen Subclass- und Subtyp-Überprüfungen
DE60008516D1 (de) Verfahren und Vorrichtung zum Mischen von Fluiden
DE60227349D1 (de) Gerät und verfahren zum austragen von dampf und flüssigkeit
DE60232627D1 (de) Verfahren und Vorrichtung zur Leistungsreduzierung in Schaltungen mit geschalteten Kapazitäten
DE50104357D1 (de) Vorrichtung und Verfahren zum Herstellen von Dichtungslagen
DE60206714D1 (de) Vorrichtung und Verfahren zum Testen von PLL-Schaltungen
DE50102937D1 (de) Verfahren zum betrieb eines elektromagnetischen schaltgeräts und elektromagnetisches schaltgerät
DE60318432D1 (de) Verfahren und vorrichtungen zum umsetzen von farbwerten
DE50114463D1 (de) Integrierte Schaltung mit Testbetriebsart und Verfahren zum Testen einer Vielzahl solcher integrierter Schaltungen
DE10196409T1 (de) System und Verfahren zum Vergleich von Elektronikfertigungsdaten
DE50015577D1 (de) Verfahren zum betrieb einer mischpotential-abgassonde und schaltungsanordnungen zur durchführung der verfahren
DE60221319D1 (de) Verfahren und Apparat für Speicheranordnungen
ATE248236T1 (de) Verfahren zum entchromen und/oder entnickeln von flüssigen schlacken

Legal Events

Date Code Title Description
8364 No opposition during term of opposition