DE60202856D1 - Methode und system zur automatischen verzögerungserkennung und empfängeranpassung für eine synchrone busschnittstelle - Google Patents

Methode und system zur automatischen verzögerungserkennung und empfängeranpassung für eine synchrone busschnittstelle

Info

Publication number
DE60202856D1
DE60202856D1 DE60202856T DE60202856T DE60202856D1 DE 60202856 D1 DE60202856 D1 DE 60202856D1 DE 60202856 T DE60202856 T DE 60202856T DE 60202856 T DE60202856 T DE 60202856T DE 60202856 D1 DE60202856 D1 DE 60202856D1
Authority
DE
Germany
Prior art keywords
bus interface
delay detection
automatic delay
synchronous bus
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60202856T
Other languages
English (en)
Other versions
DE60202856T2 (de
Inventor
Yang Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE60202856D1 publication Critical patent/DE60202856D1/de
Publication of DE60202856T2 publication Critical patent/DE60202856T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
DE60202856T 2001-04-02 2002-03-28 Methode und system zur automatischen verzögerungserkennung und empfängeranpassung für eine synchrone busschnittstelle Expired - Lifetime DE60202856T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US824389 2001-04-02
US09/824,389 US6892314B2 (en) 2001-04-02 2001-04-02 Method and system of automatic delay detection and receiver adjustment for synchronous bus interface
PCT/EP2002/004875 WO2002080414A2 (en) 2001-04-02 2002-03-28 A method and system of automatic delay detection and receiver adjustment for synchronous bus interface

Publications (2)

Publication Number Publication Date
DE60202856D1 true DE60202856D1 (de) 2005-03-10
DE60202856T2 DE60202856T2 (de) 2006-02-09

Family

ID=25241277

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60202856T Expired - Lifetime DE60202856T2 (de) 2001-04-02 2002-03-28 Methode und system zur automatischen verzögerungserkennung und empfängeranpassung für eine synchrone busschnittstelle

Country Status (9)

Country Link
US (1) US6892314B2 (de)
EP (1) EP1374077B1 (de)
JP (1) JP3966511B2 (de)
KR (1) KR100543646B1 (de)
AT (1) ATE288599T1 (de)
AU (1) AU2002304613A1 (de)
DE (1) DE60202856T2 (de)
TW (1) TW561330B (de)
WO (1) WO2002080414A2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7089518B2 (en) * 2004-05-08 2006-08-08 International Business Machines Corporation Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks
US7299436B2 (en) * 2005-02-10 2007-11-20 International Business Machines Corporation System and method for accurately modeling an asynchronous interface using expanded logic elements
JP4701244B2 (ja) * 2005-06-10 2011-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーション マイクロコンピュータ及びそのテスト方法
US20070098020A1 (en) * 2005-10-27 2007-05-03 Yee Ja Methods and arrangements to model an asynchronous interface
US7886085B2 (en) 2006-04-05 2011-02-08 Panasonic Corporation Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal
US7900079B2 (en) * 2006-08-11 2011-03-01 International Business Machines Corporation Data capture window synchronizing method for generating data bit sequences and adjusting capture window on parallel data paths
US8027421B2 (en) * 2006-09-21 2011-09-27 Analog Devices, Inc. Serial digital data communication interface for transmitting data bits each having a width of multiple clock cycles
EP2341445B1 (de) * 2009-12-30 2017-09-06 Intel Deutschland GmbH Verfahren zur Hochgeschwindigkeits-Datenübertragung
US8782459B2 (en) 2011-06-21 2014-07-15 Via Technologies, Inc. Apparatus and method for advanced synchronous strobe transmission
US8839018B2 (en) 2011-06-21 2014-09-16 Via Technologies, Inc. Programmable mechanism for optimizing a synchronous data bus
US8751851B2 (en) 2011-06-21 2014-06-10 Via Technologies, Inc. Programmable mechanism for synchronous strobe advance
US8751850B2 (en) 2011-06-21 2014-06-10 Via Technologies, Inc. Optimized synchronous data reception mechanism
US8751852B2 (en) 2011-06-21 2014-06-10 Via Technologies, Inc. Programmable mechanism for delayed synchronous data reception
US8683253B2 (en) 2011-06-21 2014-03-25 Via Technologies, Inc. Optimized synchronous strobe transmission mechanism
US8782460B2 (en) 2011-06-21 2014-07-15 Via Technologies, Inc. Apparatus and method for delayed synchronous data reception
US9552320B2 (en) 2013-01-22 2017-01-24 Via Technologies, Inc. Source synchronous data strobe misalignment compensation mechanism
US8886855B2 (en) 2013-01-22 2014-11-11 Via Technologies, Inc. Apparatus and method for dynamic alignment of source synchronous bus signals
US9557765B2 (en) 2013-01-22 2017-01-31 Via Technologies, Inc. Mechanism for automatically aligning data signals and strobe signals on a source synchronous bus
TWI522809B (zh) * 2013-01-22 2016-02-21 威盛電子股份有限公司 補償同步資料匯流排之誤差的裝置與方法
US9319035B2 (en) 2013-01-22 2016-04-19 Via Technologies, Inc. Source synchronous bus signal alignment compensation mechanism
US10284361B2 (en) 2017-05-05 2019-05-07 Mediatek Inc. Channel skew calibration method and associated receiver and system
CN115129639B (zh) * 2022-06-14 2023-10-27 沐曦集成电路(南京)有限公司 Axi总线的延时调整装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3784907A (en) 1972-10-16 1974-01-08 Ibm Method of propagation delay testing a functional logic system
US5280629A (en) * 1991-12-06 1994-01-18 Motorola, Inc. Technique for measuring channel delay
US5465346A (en) 1991-12-30 1995-11-07 Dell Usa, L.P. Method and apparatus for synchronous bus interface optimization
CA2099415A1 (en) 1992-08-27 1994-02-28 Duane Rodney Aadsen Method and apparatus for self-testing of delay faults
US5509038A (en) 1994-04-06 1996-04-16 Hal Computer Systems, Inc. Multi-path data synchronizer system and method
JPH1131964A (ja) * 1997-07-11 1999-02-02 Hitachi Ltd 論理回路
US6105144A (en) * 1998-03-02 2000-08-15 International Business Machines Corporation System and method for alleviating skew in a bus
JP2002135234A (ja) * 2000-10-20 2002-05-10 Mitsubishi Electric Corp スキュー調整回路

Also Published As

Publication number Publication date
WO2002080414A3 (en) 2003-10-30
US6892314B2 (en) 2005-05-10
ATE288599T1 (de) 2005-02-15
DE60202856T2 (de) 2006-02-09
TW561330B (en) 2003-11-11
EP1374077A2 (de) 2004-01-02
JP3966511B2 (ja) 2007-08-29
JP2004530203A (ja) 2004-09-30
KR20030088034A (ko) 2003-11-15
AU2002304613A1 (en) 2002-10-15
KR100543646B1 (ko) 2006-01-20
WO2002080414A2 (en) 2002-10-10
US20020144189A1 (en) 2002-10-03
EP1374077B1 (de) 2005-02-02

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8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7