US20070098020A1 - Methods and arrangements to model an asynchronous interface - Google Patents

Methods and arrangements to model an asynchronous interface Download PDF

Info

Publication number
US20070098020A1
US20070098020A1 US11260557 US26055705A US2007098020A1 US 20070098020 A1 US20070098020 A1 US 20070098020A1 US 11260557 US11260557 US 11260557 US 26055705 A US26055705 A US 26055705A US 2007098020 A1 US2007098020 A1 US 2007098020A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
pattern
skews
time interval
bit lines
skew
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11260557
Inventor
Yee Ja
Bradley Nelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Abstract

Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may then alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, changes to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

Description

    FIELD OF INVENTION
  • The present invention is in the field of clock circuits. More particularly, the present invention relates to methods and arrangements to model behavior of an asynchronous interface.
  • BACKGROUND
  • The push for high speed computing has led to the development of high speed, time-constrained, asynchronous links such as IBM's self-timed interfaces (STIs). In fact, the STI has been implemented in IBM's largest servers for several generations, providing successively improved input-output (I/O) subsystem bandwidth capacities. Time-constrained, asynchronous links are asynchronous data interfaces that transmit data over parallel bit lines via independent clock signals that are substantially synchronized at times. In particular, time-constrained, asynchronous interfaces, sometimes referred to as elastic or semi-static interfaces, may guarantee synchronous behavior over a specified time interval to facilitate data transfers.
  • For purposes of the data transfers, the synchronous nature of the elastic interfaces is limited to a time interval following the initial transmission and receipt of a test pattern of data. The test pattern data is examined to determine the timing relationship or skew pattern between bits received via different bit lines of the bus. Thereafter, for the extent of the time interval, data crossing the interface may be presumed to follow the same skew pattern. Receive logic identifies the skew pattern based upon the test pattern data and determines the timing required to synchronously capture subsequent data sent across the same interface.
  • Elastic interfaces make use of the knowledge that the change in phase between independently driven clocks will occur over time and that the rate of change is fairly constant. In particular, clocks for the elastic interface will stay reasonably in phase for the time interval and, thus, for that time interval, the clocks can be viewed as being effectively synchronous for data transfers. However, after the expiration of the time interval, the elastic interface is asynchronous again.
  • When testing circuit performance with regards to communication across an elastic interface, circuit designers must verify that the circuit can transfer data during the specified time intervals. Otherwise, the circuit will not function properly.
  • To verify the circuit's performance, designers utilize circuit simulators to simulate the circuit's performance prior to the investment of large amounts of capital to build the circuit. Ideally, circuit simulations accurately simulate every potentially problematic aspect of the circuit operation. The problem with current circuit simulators from the perspective of the elastic interface is that skew/jitter logic is employed to model asynchronous behavior. The skew/jitter logic is non-deterministic—i.e. the phase shift employed for a signal is always non-static. So skew/jitter logic cannot be used for elastic interfaces or other semi-static interfaces that require that the skew/jitter imposed remains static for a period of time.
  • The current solution for this problem is to employ a static skew pattern. This avoids the deficiency in circuit simulation of the elastic interface. The static skew pattern simulates one skew pattern of the elastic interface, however, this solution fails to simulate asynchronous behavior of the elastic interface at the expiration of the synchronous time interval, which is a potentially problematic aspect of the circuit operation.
  • SUMMARY OF THE INVENTION
  • The problems identified above are in large part addressed by methods and arrangements to model an asynchronous interface. One embodiment provides a method to model behavior of an asynchronous interface. The method may involve generating a first pattern of skews for a number of bit lines of the asynchronous interface and applying the first pattern of skews to bits associated with the number of bit lines during a time interval. Furthermore, the method may apply a second pattern of skews to subsequent bits associated with the number of bit lines after the time interval.
  • Another embodiment provides a system to model behavior of an asynchronous interface. The system may comprise a delay applicator to apply skews to bits crossing the asynchronous interface via a number of bit lines. The system may also comprise a delay generator to generate a first pattern of the skews for the number of bit lines during a time interval and to generate a second pattern of skews for subsequent bits crossing the asynchronous interface via the number of bit lines after the time interval.
  • Another embodiment provides machine-accessible medium containing instructions to model behavior of an asynchronous interface, which when the instructions are executed by a machine, cause said machine to perform operations. The operations may involve generating a first pattern of skews for a number of bit lines of the asynchronous interface and applying the first pattern of skews to bits associated with the number of bit lines during a time interval. The operations may further involve applying a second pattern of skews to subsequent bits associated with the number of bit lines after the time interval.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which, like references may indicate similar elements:
  • FIG. 1 depicts an embodiment of system level circuit simulation to simulate synchronous and asynchronous behavior of a 64-bit point-to-point bus between a processor and another chip;
  • FIG. 2 depicts an example of a timing diagram for transmission and receipt of bits across an N-bit point-to-point bus such as the 64-bit point-to-point bus of FIG. 1;
  • FIG. 3 depicts an embodiment of a circuit simulation for application of a skew to a bit line to simulate synchronous and asynchronous behavior of a time-constrained, asynchronous interface;
  • FIG. 4 depicts an embodiment of a staged multiplexor to equate the probabilities for selection of a skew from a set of seven different potential skews to model the behavior of a bit line of an elastic interface; and
  • FIG. 5 depicts a flowchart of an embodiment to simulate synchronous and asynchronous behavior of bit lines of an asynchronous bus.
  • DETAILED DESCRIPTION OF EMBODIMENTS
  • The following is a detailed description of embodiments of the invention depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the invention. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The detailed descriptions below are designed to make such embodiments obvious to a person of ordinary skill in the art.
  • Generally speaking, methods and arrangements to model an asynchronous interface are contemplated. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may then alter the skew pattern at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, changes to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.
  • While specific embodiments will be described below with reference to particular circuit or logic configurations, those of skill in the art will realize that embodiments of the present invention may advantageously be implemented with other substantially equivalent configurations.
  • Turning now to the drawings, FIG. 1 depicts an embodiment of system level circuit simulation 100 to simulate synchronous and asynchronous behavior of a 64-bit point-to-point bus, buses 133 and 135, between a processor 105 and another chip 140. For instance, processor 105 may model behavior of one of IBM's PowerPC 970 processors and chip 140 may model, for example, behavior of a memory controller hub designed to operate with processor 105.
  • Logic associated with transmission of data from processor 105 to chip 140 may include a synch counter 107, delay applicators 109, delay generators 111, and transmitters 115 to implement a skew pattern in data transmitted across 32-bit bus 133. In other embodiments, synch counter 107, delay applicators 109, and delay generators 111 may reside on the receiver-side of bus 133. In such embodiments, a skew pattern may be applied to the initial receive latch of receivers 142 rather than the initial send latch of transmitters 115. Furthermore, embodiments that implement a skew pattern on the send side may also model full propagation delays.
  • Synch counter 107 may count clock cycles of the time interval in which the clocks of bus 133 remain substantially in phase, referred to as a synch count, to facilitate generation of a new skew pattern upon expiration of the time interval. In some embodiments, the time interval may vary in accordance with a margin of error associated with the time interval. In further embodiments, the synch count for the time interval may be reset upon transmission of a test pattern of data.
  • While the present embodiment illustrates synch counter 107 for the send side of bus 133 and a synch counter 144 for the receive side of bus 133, other embodiments may utilize a single synch counter such as synch counter 107 for both sides of bus 133. Further embodiments may utilize synch counter 107 to indicate the end of a time interval for more than one bus such as bus 133 and bus 135. In one embodiment, other logic is implemented in place of synch counter 107 to generate a signal indicative of the end of a time interval for synchronized data transfer across an asynchronous bus like bus 133 and 135.
  • Delay applicators 109 may apply skews to data in 113 bits crossing the asynchronous interface via a number of bit lines of bus 133. In the present embodiment, several possible skews may be applied to each bit line so delay generators 111 may generate the skew pattern by selecting a signal from available signals for each bit line. In further embodiments, delay applicators 109 may apply skews to bits after selection of the skew pattern by delay generators 111. In such embodiments, for example, delay generators 111 may select skews for each bit line of bus 133 and delay applicators 109 may then apply the skew pattern to bits being transmitted across bus 133.
  • Delay generators 111 may generate a first pattern of skews for bit lines of bus 133 during a time interval. In many embodiments, delay generators 109 may generate an independent skew for each bit line of bus 133. The skew patterns may be generated by selecting skewed signals from a range of predetermined skewed signals available from delay applicators 109. The range may comprise a range of feasible skews for bus 133. For instance, delay generators 109 may generate 32 random select signals, one for each bit line of bus 133, to select from delays input from delay applicators 109. Then, upon receipt of an indication from synch counter 107 that the time interval is ending or has ended, delay generators 111 may generate new selection signals to modify the skew pattern for subsequent bits crossing bus 133 to chip 140.
  • Transmitters 115 may comprise a simulation of physical layer devices adapted to transmit bits across bus 133 to receivers 142. Similarly, receiver 142 may comprise a simulation of physical layer devices adapted to receive the bits from transmitters 115. Depending upon the parameters of the simulation, transmitters 115 and receivers 142 may simulate ideal or less ideal circuitry operation.
  • Synch counter 117, delay generators 119, and delay applicators 121 comprise logic to apply a skew pattern to bits on the receive side of bus 135. In other embodiments, chip 140 may comprise logic such as delay applicators 109 and delay generators 111 to apply the skew pattern to bits prior to transmitting the bits across bus 135.
  • In the present embodiment, transmitters 150 transmit data across bus 135 to receivers 123 without skews related to, e.g., differences in temperature and voltage between bit lines of the bus, differences in length of the bit lines, or the like. In further embodiments, one or more of these skews or other skews may be applied to the bits crossing bus 135 prior to transmission from chip 140.
  • Delay applicators 121 may receive the bits and add a number of different skews to each bit between the overall minimum and maximum latencies expected for the bit lines of bus 135. Applying skews between the minimum and maximum skews at delay applicators 121 advantageously avoids the necessity, in some embodiments, of separate logic for modeling a zero clock cycle skew.
  • Delay generators 119 may randomly select a skew pattern for the bits from those provided by delay applicators 121 based upon an indication from synch counter 117. The indication from synch counter 117 may be related to the transmission of test pattern data across bus 135 and/or the end of a substantially synchronous time interval for bus 135. Then delay generators 119 may forward the bits to a skew pattern determiner 129.
  • Synch counter 117 may perform a substantially similar function as synch counter 107 for bus 135. In some embodiments, synch counter 117 may comprise logic adapted to decrement a synch count from an initial number to zero and, upon reaching zero, transmit a signal to delay generators 119 to select a new skew pattern. In other embodiments, synch counter 117 may comprise part of other logic designed for a different and/or related purpose.
  • Synch counter 125 may generate a signal to indicate the end of a substantially synchronous time interval for data transfer across bus 135. Synch counter 125 may comprise logic to simulate differences potentially encountered between signals received at delay generators 119 and signals received at skew pattern determiner 129. In other embodiments, skew pattern generator 129 may receive signals to indicate the end of substantially synchronous time intervals for data transfer across bus 135 from synch counter 117.
  • Skew pattern determiner 129 may receive an indication from synch counter 125 to demark the end of a first time interval of substantially synchronous behavior. Skew pattern determiner 129 may then, in response to receipt of a new test pattern of bits, determine a new skew pattern for data transferred across bus 135 during a second time interval of substantially synchronous behavior. The new skew pattern may be stored in current skew pattern 127 and utilized to organize data received during the second time interval.
  • Skew pattern determiner 129 may then apply the current skew pattern for the bit lines during the second time interval of substantially synchronous behavior and transmit the data to other logic via data out 131. Current skew pattern 127 may comprise memory or logic to maintain the most recent valid skew pattern for the bits crossing bus 135.
  • Chip 140 may be a simulation of a companion chip for processor 105 such as a memory controller hub, a host bridge, a snoop controller, or the like. Synch counter 144, skew pattern determiner 146, and current skew pattern 148 may model receipt and interpretation of data received from transmitters 115 in a manner similar to that of synch counter 125, skew pattern determiner 129, and current skew pattern 127.
  • FIG. 2 depicts an example of a timing diagram 200 for transmission and receipt of bits across a bus such as the 64-bit point-to-point bus of FIG. 1. The timing diagram 200 depicts increments in skew delay in relation to a series latches from latch 1 to latch N. The skew associated with latch 1 may be, for instance, a single clock cycle of delay for bit lines marked with an ‘X’ in the column of latch 1. In other embodiments, the skew associated with latch 1 may be a zero clock cycle delay to simulate no skew or a negative skew, depending upon the time reference associated with the latches. In further embodiments, latches may represent two or more clock cycles of delay.
  • In the present embodiment, latch 1 represents a zero skew and each successive latch, 2 through N, represents the addition of a single clock cycle of delay. Thus, latch 2 represents a single clock cycle of delay and latch N represents a clock delay of N−1 clock cycles. For example, the ‘X’ in the row of bit line 1 is under latch one to indicate a zero clock cycle delay for bits received via bit line 1 and the ‘X’ in the row of bit line N is in the latch 2 column to indicate that bits received via bit line N will have a single clock cycle skew. Similarly, an ‘X’ in the latch 3 column indicates a skew of two clock cycles for bits received via bit line 2 and each ‘X’ in the latch 4 column indicates skews of three clock cycles for bits received via bit lines 3 and 4.
  • The combination of the clock skews for the bus comprising bit lines 1 through N is an example of a skew pattern. The skew pattern may be determined by comparing the skew of bits of test pattern data transmitted across the bus. For instance, the test pattern data on each bit line may propagate through a series of latches until all the test pattern data is received. Once the test pattern data is received, the relative progression of the bits of the test pattern data through the series of latches may indicate the skew pattern.
  • Turning now to FIG. 3, there is shown an embodiment of a circuit simulation 300 for application of a skew to a bit line to simulate synchronous and asynchronous behavior of a time-constrained, asynchronous interface. The circuit simulation 300 includes a synch counter 310, a delay generator 330, and a delay applicator 340 to model the behavior. For instance, synch counter 310 is adapted to count a number of cycles, a synch count, which may be the number of cycles that synchronous behavior is specified or guaranteed for the asynchronous interface. The synch count is reset when test pattern data is transmitted across the asynchronous interface by producing a reset signal 316. The reset signal 316 is produced in response to application of a logical one at an input 305, which is indicative of the test data being sent.
  • The logical one is applied to an input of ‘OR’ logic 312. The second input of ‘OR’ logic 312 is the output signal 326 of synch counter 310, which remains a logical zero until the end of the synch count. Interval counter 320 may decrement the synch count down to zero or count from zero to the synch count. In some embodiments, the synch count is fixed. In other embodiments, the synch count, which is counted by interval counter 320, may be changed periodically. The reset signal 316 restarts the synch count.
  • Once interval counter 320 completes the synch count, a skew interval 322 receives a signal indicating that the time interval for substantially synchronous behavior of the asynchronous interface has expired. In response to the signal, skew interval 322 transmits a signal 326 to delay generator 330 and possibly to other delay generators for other bit lines associated with the same bus or another bus.
  • Delay generator 330 comprises random logic 332 and multiplexor 334. Random logic 332 may generate a substantially random selection signal for multiplexor 334. In some embodiments, the selection signal generated by random logic 332 may be selected from equally weighted selection signals. In other embodiments, the selection signals may be weighted differently.
  • The selection signal may comprise one or more bits and multiplexor 334 may select an input from delay applicator 340 based upon the selection signal. The selection of an input from delay applicator 340 in this embodiment selects a bit that is delayed by a skew. In many embodiments, each input from delay applicator 340 may comprise the bit delayed by a different skew and the skews may range, e.g., from a zero skew to a maximum skew for the corresponding bit line of the asynchronous bus. In further embodiments, a zero skew option may not be available so the skews may vary from a minimum skew to a maximum skew. In still other embodiments, the minimum skew available may be less than a zero skew or a negative skew, depending upon parameters of the simulation, time references selected for the latches, or evaluative tools for the logic.
  • Random logic 332 maintains the same signal at the input of multiplexor 334 until a signal is received from synch counter 310 to generate a subsequent selection signal. Then, the subsequent selection signal may be the same or different from the prior selection signal in some embodiment. As a result, delay generator 330 selects the same skew for subsequent bits until random logic 332 generates a new selection signal.
  • Delay applicator 340 may receive a bit of bit line data and apply a number of different delays to the bit. Each delay, which is within a selected range of skews for the bit line, is input into multiplexor 334. To illustrate the present embodiment, assume that latches 342 through 348 each add a one clock cycle delay to a bit received at the bit line data input of latch 342. In other words, the bit is propagated latch to latch toward latch N through the latches. Selection of the output of latch 342 via multiplexor 334 provides the bit with a one clock cycle skew. Similarly, the output of latch 344 provides a two cycle delay, the output of latch 346 provides a three cycle skew, and the output of latch 348 provides an N cycle skew. Latch 350, if enabled via the enable input, provides the bit line data with a zero cycle skew as an input to multiplexor 334.
  • FIG. 4 illustrates an embodiment of a staged multiplexor 400 to equate the probabilities for selection of a skew from a set of seven different potential skews 405, 425, and 440 to model the behavior of a bit line of an elastic interface. Staged multiplexor 400 or another staged multiplexor may be implemented in place of multiplexor 334 of FIG. 3 to handle a number of inputs received from delay applicator 340 of FIG. 3 that is not a power of two.
  • Multiplexor (MUX) 420 receives four inputs 405 from, e.g., a delay applicator and two selection signals 410 and 415 from, e.g., a random logic. The selection signals each have an equal chance “1/1” of being a logical one or a logical zero. “1/1” represents the weighting of a logical zero and a logical one.
  • Similarly, MUX 435 selects between two inputs 425. Selection signal 430 provides a 50% chance of being a logical zero and a 50% chance of being a logical one as indicated by “1/1”. Then, the selected outputs of MUX 420 and MUX 435 are input into MUX 450. MUX 450 receives a selection signal 445 that has a one in three chance “1/3” of selecting a logical zero over a logical one and, as a result, provides equivalent probabilities of selecting each of the inputs 405 and 425.
  • After selecting from inputs 405 and 425, the selected input is applied to an input of MUX 460. The seventh possible input 440 is also applied to an input of MUX 460. MUX 460 then receives a selection signal 455 that provides a one in seven chance “1/7” of selecting the input 440. The selected input from the seven inputs is then sent to other logic via output 465.
  • Referring now to FIG. 5, there is shown a flowchart of an embodiment to simulate synchronous and asynchronous behavior of bit lines of an asynchronous bus. Flow chart 500 begins with resetting a time interval count, or synch count, in response to sending test pattern data (element 510). For example, during initialization of a time interval of substantially synchronous data transfer on the asynchronous bus, test pattern data is transmitted across the bus to determine a skew pattern for data crossing the bus. As the test pattern data is transmitted across the bus, the time interval count down for substantially synchronous behavior is restarted.
  • A counter may decrement the time interval count each clock cycle (element 515) until the interval expires (element 520). Once the time interval count reaches zero, the counter signals logic to generate a random select signal (element 525), which is applied to a select input of, e.g., a multiplexor, a multi-stage multiplexor, or similar logic. The multiplexor may then select a skew for a bit line of the asynchronous bus based upon the random select signal (element 530). For example, the multiplexor may comprise several inputs for the bit and each input may add a different amount of delay or skew to transmission of the bit across the asynchronous bus. The random select signal may then facilitate selection of one of those skews in a substantially non-deterministic manner. In other embodiments, selection of one of those skews may follow a heuristic or other dynamic or pre-determined pattern. Then, when the time interval for substantially synchronous behavior expires, the multiplexor receives a new select signal to modify the skew pattern again in a substantially non-deterministic manner, advantageously modeling the behavior of the time-constrained, asynchronous bus.
  • If there are additional bit lines of the bus (element 540), a substantially non-deterministic skew may be selected for each by generating random select signals (element 525), selecting skews for each based upon the random select signals (element 530), and applying the skews to data crossing the bit lines of the bus (element 535). Furthermore, if the circuit simulation is to continue (element 545), each element of flowchart 500 from element 510 to element 540 may be repeated. Otherwise, the circuit simulation may end.
  • Another embodiment of the invention is implemented as a program product for implementing a circuit simulation such as circuit simulation 100 illustrated in FIG. 1. The program(s) of the program product defines functions of the embodiments (including the methods described herein) and can be contained on a variety of data and/or signal-bearing media. Illustrative data and/or signal-bearing media include, but are not limited to: (i) information permanently stored on non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive); (ii) alterable information stored on writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive); and (iii) information conveyed to a computer by a communications medium, such as through a computer or telephone network, including wireless communications. The latter embodiment specifically includes information downloaded from the Internet and other networks. Such data and/or signal-bearing media, when carrying computer-readable instructions that direct the functions of the present invention, represent embodiments of the present invention.
  • In general, the routines executed to implement the embodiments of the invention, may be part of an operating system or a specific application, component, program, module, object, or sequence of instructions. The computer program of the present invention typically is comprised of a multitude of instructions that will be translated by a computer into a machine-readable format and hence executable instructions. Also, programs are comprised of variables and data structures that either reside locally to the program or are found in memory or on storage devices. In addition, various programs described hereinafter may be identified based upon the application for which they are implemented in a specific embodiment of the invention. However, it should be appreciated that any particular program nomenclature that follows is used merely for convenience, and thus the invention should not be limited to use solely in any specific application identified and/or implied by such nomenclature.
  • It will be apparent to those skilled in the art having the benefit of this disclosure that the present invention contemplates methods and arrangements to model behavior of an asynchronous interface. It is understood that the form of the invention shown and described in the detailed description and the drawings are to be taken merely as examples. It is intended that the following claims be interpreted broadly to embrace all the variations of the example embodiments disclosed.
  • Although the present invention and some of its advantages have been described in detail for some embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Although an embodiment of the invention may achieve multiple objectives, not every embodiment falling within the scope of the attached claims will achieve every objective. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

  1. 1. A method to model behavior of an asynchronous interface, the method comprising:
    generating a first pattern of skews for a number of bit lines of the asynchronous interface;
    applying the first pattern of skews to bits associated with the number of bit lines during a time interval; and
    applying a second pattern of skews to subsequent bits associated with the number of bit lines after the time interval.
  2. 2. The method of claim 1, further comprising determining a skew pattern between the number of bit lines based upon comparison between bits of a test pattern and a pattern of received bits.
  3. 3. The method of claim 1, further comprising counting clock cycles of the time interval and resetting the time interval upon transmission of a test pattern of bits.
  4. 4. The method of claim 1, wherein generating the first pattern comprises generating a selection signal for a multiplexor logic to select a skew for at least one of the bit lines.
  5. 5. The method of claim 4, wherein generating the first pattern comprises selecting the skew from a set of skews via the multiplexor logic based upon the selection signal, wherein a probability of selection of the skew from the set of skews is predetermined.
  6. 6. The method of claim 1, wherein applying the first pattern comprises applying the first pattern prior to transmission of data across the asynchronous interface.
  7. 7. The method of claim 1, wherein applying the first pattern comprises applying the first pattern upon receipt of data at a receiver from the asynchronous interface.
  8. 8. The method of claim 1, wherein applying the second pattern of skews comprises generating the second pattern of skews.
  9. 9. The method of claim 7, wherein generating the second pattern of skews comprises selecting skews for each of the number of bit lines in a substantially non-deterministic manner.
  10. 10. A system to model behavior of an asynchronous interface, the system comprising:
    a delay applicator to apply skews to bits crossing the asynchronous interface via a number of bit lines; and
    a delay generator to generate a first pattern of the skews for the number of bit lines during a time interval and to generate a second pattern of skews for subsequent bits crossing the asynchronous interface via the number of bit lines after the time interval.
  11. 11. The system of claim 10, further comprising a synch counter to count clock cycles of the time interval to indicate an end of the time interval and to restart the time interval upon transmission of test pattern data.
  12. 12. The system of claim 10, wherein the delay applicator comprises delay logic to apply the skews prior to transmission of the bits across the asynchronous interface.
  13. 13. The system of claim 10, wherein the delay applicator comprises delay logic to apply the skews after receipt of the bits from the bit lines.
  14. 14. The system of claim 11, wherein the delay generator couples with the synch counter to generate the second pattern of skews upon expiration of the time interval, wherein the second pattern of skews is substantially non-deterministic.
  15. 15. The system of claim 10, wherein the delay generator comprises random logic to generate a selection signal for a multiplexor logic to select from the skews applied to the bits crossing the asynchronous interface for at least one of the bit lines.
  16. 16. The system of claim 15, wherein the delay generator comprises the multiplexor logic to select from the skews applied to the bits crossing the asynchronous interface based upon the selection signal, wherein a probability of selection of a skew from the skews is predetermined.
  17. 17. The system of claim 15, wherein the multiplexor logic is adapted to independently select a skew from the skews for each of the number of bit lines.
  18. 18. A machine-accessible medium containing instructions to model behavior of an asynchronous interface, which when the instructions are executed by a machine, cause said machine to perform operations, comprising:
    generating a first pattern of skews for a number of bit lines of the asynchronous interface;
    applying the first pattern of skews to bits associated with the number of bit lines during a time interval; and
    applying a second pattern of skews to subsequent bits associated with the number of bit lines after the time interval.
  19. 19. The machine-accessible medium of claim 18, wherein the operations further comprise counting clock cycles of the time interval and resetting the time interval upon transmission of a test pattern of bits.
  20. 20. The machine-accessible medium of claim 18, wherein the operations further comprise determining a skew pattern between the number of bit lines based upon comparison between bits of a test pattern and a pattern of received bits.
US11260557 2005-10-27 2005-10-27 Methods and arrangements to model an asynchronous interface Abandoned US20070098020A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11260557 US20070098020A1 (en) 2005-10-27 2005-10-27 Methods and arrangements to model an asynchronous interface

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11260557 US20070098020A1 (en) 2005-10-27 2005-10-27 Methods and arrangements to model an asynchronous interface
CN 200610142992 CN100452064C (en) 2005-10-27 2006-10-26 Methods and system to model arrangements of asynchronous interface
US12058660 US7995619B2 (en) 2005-10-27 2008-03-28 Methods and arrangements to model an asynchronous interface

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12058660 Continuation US7995619B2 (en) 2005-10-27 2008-03-28 Methods and arrangements to model an asynchronous interface

Publications (1)

Publication Number Publication Date
US20070098020A1 true true US20070098020A1 (en) 2007-05-03

Family

ID=37996226

Family Applications (2)

Application Number Title Priority Date Filing Date
US11260557 Abandoned US20070098020A1 (en) 2005-10-27 2005-10-27 Methods and arrangements to model an asynchronous interface
US12058660 Expired - Fee Related US7995619B2 (en) 2005-10-27 2008-03-28 Methods and arrangements to model an asynchronous interface

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12058660 Expired - Fee Related US7995619B2 (en) 2005-10-27 2008-03-28 Methods and arrangements to model an asynchronous interface

Country Status (2)

Country Link
US (2) US20070098020A1 (en)
CN (1) CN100452064C (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080165914A1 (en) * 2007-01-10 2008-07-10 Broadcom Corporation System and Method for Managing Counters
US20090063922A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module
US20090063729A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel
US20090063923A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System and Method for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel
US20090063730A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel
US20090063784A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Enhancing the Memory Bandwidth Available Through a Memory Module
US20090063761A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C Buffered Memory Module Supporting Two Independent Memory Channels
US20090063731A1 (en) * 2007-09-05 2009-03-05 Gower Kevin C Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel
US20090063787A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity
US20090193201A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Increase the Overall Bandwidth of a Memory Channel By Allowing the Memory Channel to Operate at a Frequency Independent from a Memory Device Frequency
US20090193315A1 (en) * 2008-01-24 2009-07-30 Gower Kevin C System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel
US20090193200A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Support a Full Asynchronous Interface within a Memory Hub Device
US20090190427A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Enable a Memory Hub Device to Manage Thermal Conditions at a Memory Device Level Transparent to a Memory Controller
US20090193203A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency
US20090193290A1 (en) * 2008-01-24 2009-07-30 Arimilli Ravi K System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem
US20110004709A1 (en) * 2007-09-05 2011-01-06 Gower Kevin C Method for Enhancing the Memory Bandwidth Available Through a Memory Module
US7899983B2 (en) 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7930469B2 (en) 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US20170300434A1 (en) * 2013-10-23 2017-10-19 Intel Corporation Emi mitigation on high-speed lanes using false stall

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9552320B2 (en) 2013-01-22 2017-01-24 Via Technologies, Inc. Source synchronous data strobe misalignment compensation mechanism
US9319035B2 (en) * 2013-01-22 2016-04-19 Via Technologies, Inc. Source synchronous bus signal alignment compensation mechanism
US9557765B2 (en) 2013-01-22 2017-01-31 Via Technologies, Inc. Mechanism for automatically aligning data signals and strobe signals on a source synchronous bus

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5553276A (en) * 1993-06-30 1996-09-03 International Business Machines Corporation Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units
US5598113A (en) * 1995-01-19 1997-01-28 Intel Corporation Fully asynchronous interface with programmable metastability settling time synchronizer
US5901116A (en) * 1994-05-02 1999-05-04 Colorado Seminary Programmable timing unit for generating multiple coherent timing signals
US20020013875A1 (en) * 1999-03-05 2002-01-31 International Business Machines Corporation Elastic interface apparatus and method therefor
US20020144189A1 (en) * 2001-04-02 2002-10-03 International Business Machines Corporation Method and system of automatic delay detection and receiver adjustment for synchronous bus interface
US20030046596A1 (en) * 2001-09-05 2003-03-06 International Business Machines Corp. Data processing system and method with dynamic idle for tunable interface calibration
US20030101015A1 (en) * 2001-11-29 2003-05-29 International Business Machines Corpaoation Method and apparatus for testing, characterizing and tuning a chip interface
US20050069068A1 (en) * 2003-09-29 2005-03-31 International Business Machines Corporation Asynchronous interface methods and apparatus
US6876678B1 (en) * 1999-02-04 2005-04-05 Cisco Technology, Inc. Time division multiplexing method and apparatus for asynchronous data stream
US20050122810A1 (en) * 2003-12-04 2005-06-09 Jung-Bae Lee Methods and systems for dynamically selecting word line off times and/or bit line equalization start times in memory devices
US20050251773A1 (en) * 2004-05-08 2005-11-10 International Business Machines Corporation Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks
US20060233291A1 (en) * 2003-04-09 2006-10-19 Garlepp Bruno W Partial response receiver with clock data recovery
US20080201599A1 (en) * 2005-02-11 2008-08-21 Ferraiolo Frank D Combined alignment scrambler function for elastic interface

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392227A (en) 1992-07-24 1995-02-21 Logic Modeling Corporation System and method for generating electronic circuit simulation models having improved accuracy
CN1303811C (en) 2004-11-16 2007-03-07 熊猫电子集团有限公司 Searching method for TV programme signal

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5553276A (en) * 1993-06-30 1996-09-03 International Business Machines Corporation Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units
US5901116A (en) * 1994-05-02 1999-05-04 Colorado Seminary Programmable timing unit for generating multiple coherent timing signals
US5598113A (en) * 1995-01-19 1997-01-28 Intel Corporation Fully asynchronous interface with programmable metastability settling time synchronizer
US6876678B1 (en) * 1999-02-04 2005-04-05 Cisco Technology, Inc. Time division multiplexing method and apparatus for asynchronous data stream
US20020013875A1 (en) * 1999-03-05 2002-01-31 International Business Machines Corporation Elastic interface apparatus and method therefor
US20020144189A1 (en) * 2001-04-02 2002-10-03 International Business Machines Corporation Method and system of automatic delay detection and receiver adjustment for synchronous bus interface
US20030046596A1 (en) * 2001-09-05 2003-03-06 International Business Machines Corp. Data processing system and method with dynamic idle for tunable interface calibration
US20030101015A1 (en) * 2001-11-29 2003-05-29 International Business Machines Corpaoation Method and apparatus for testing, characterizing and tuning a chip interface
US20060233291A1 (en) * 2003-04-09 2006-10-19 Garlepp Bruno W Partial response receiver with clock data recovery
US20050069068A1 (en) * 2003-09-29 2005-03-31 International Business Machines Corporation Asynchronous interface methods and apparatus
US20050122810A1 (en) * 2003-12-04 2005-06-09 Jung-Bae Lee Methods and systems for dynamically selecting word line off times and/or bit line equalization start times in memory devices
US20050251773A1 (en) * 2004-05-08 2005-11-10 International Business Machines Corporation Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks
US20080201599A1 (en) * 2005-02-11 2008-08-21 Ferraiolo Frank D Combined alignment scrambler function for elastic interface

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8417810B2 (en) * 2007-01-10 2013-04-09 Broadcom Corporation System and method for managing counters
US20080165914A1 (en) * 2007-01-10 2008-07-10 Broadcom Corporation System and Method for Managing Counters
US7584308B2 (en) 2007-08-31 2009-09-01 International Business Machines Corporation System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel
US20090063923A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System and Method for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel
US20090063730A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel
US20090063784A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Enhancing the Memory Bandwidth Available Through a Memory Module
US20090063761A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C Buffered Memory Module Supporting Two Independent Memory Channels
US7840748B2 (en) 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
US20090063787A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity
US7818497B2 (en) 2007-08-31 2010-10-19 International Business Machines Corporation Buffered memory module supporting two independent memory channels
US20090063729A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel
US8086936B2 (en) 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US8082482B2 (en) 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US20090063922A1 (en) * 2007-08-31 2009-03-05 Gower Kevin C System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module
US7899983B2 (en) 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7865674B2 (en) 2007-08-31 2011-01-04 International Business Machines Corporation System for enhancing the memory bandwidth available through a memory module
US7861014B2 (en) 2007-08-31 2010-12-28 International Business Machines Corporation System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
US20110004709A1 (en) * 2007-09-05 2011-01-06 Gower Kevin C Method for Enhancing the Memory Bandwidth Available Through a Memory Module
US8019919B2 (en) 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US7558887B2 (en) 2007-09-05 2009-07-07 International Business Machines Corporation Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel
US20090063731A1 (en) * 2007-09-05 2009-03-05 Gower Kevin C Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel
US7770077B2 (en) 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US20090193290A1 (en) * 2008-01-24 2009-07-30 Arimilli Ravi K System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem
US20090193203A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency
US7925826B2 (en) 2008-01-24 2011-04-12 International Business Machines Corporation System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency
US7925824B2 (en) 2008-01-24 2011-04-12 International Business Machines Corporation System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
US7925825B2 (en) 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
US7930469B2 (en) 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US7930470B2 (en) 2008-01-24 2011-04-19 International Business Machines Corporation System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller
US20090190427A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Enable a Memory Hub Device to Manage Thermal Conditions at a Memory Device Level Transparent to a Memory Controller
US20090193200A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Support a Full Asynchronous Interface within a Memory Hub Device
US20090193315A1 (en) * 2008-01-24 2009-07-30 Gower Kevin C System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel
US8140936B2 (en) 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US20090193201A1 (en) * 2008-01-24 2009-07-30 Brittain Mark A System to Increase the Overall Bandwidth of a Memory Channel By Allowing the Memory Channel to Operate at a Frequency Independent from a Memory Device Frequency
US20170300434A1 (en) * 2013-10-23 2017-10-19 Intel Corporation Emi mitigation on high-speed lanes using false stall

Also Published As

Publication number Publication date Type
CN1959686A (en) 2007-05-09 application
US7995619B2 (en) 2011-08-09 grant
CN100452064C (en) 2009-01-14 grant
US20080192645A1 (en) 2008-08-14 application

Similar Documents

Publication Publication Date Title
US6571204B1 (en) Bus modeling language generator
US7797575B2 (en) Triple voting cell processors for single event upset protection
US20040068682A1 (en) Deskew circuit and disk array control device using the deskew circuit, and deskew method
US20110078350A1 (en) Method for generating multiple serial bus chip selects using single chip select signal and modulation of clock signal frequency
US7246274B2 (en) Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER)
US20060053328A1 (en) Training pattern based de-skew mechanism and frame alignment
US20020059052A1 (en) Co-simulation of network components
US20060168456A1 (en) Method and apparatus to generate circuit energy models with multiple clock gating inputs
US20090171647A1 (en) Interconnect architectural state coverage measurement methodology
US7421637B1 (en) Generating test input for a circuit
US20030123588A1 (en) Synchronizing data or signal transfer across clocked logic domains
US20130329503A1 (en) Command paths, apparatuses, memories, and methods for providing internal commands to a data path
US7206958B1 (en) Determining cycle adjustments for static timing analysis of multifrequency circuits
US20050209839A1 (en) Data processing apparatus simulation
CN102648453A (en) Distributed multi-core memory initialization
US20130155788A1 (en) Ddr 2d vref training
US7386827B1 (en) Building a simulation environment for a design block
US6507808B1 (en) Hardware logic verification data transfer checking apparatus and method therefor
US7484192B2 (en) Method for modeling metastability decay through latches in an integrated circuit model
US20100242003A1 (en) Hierarchical Verification Of Clock Domain Crossings
US20090112551A1 (en) Matrix modeling of parallel data structures to facilitate data encoding and/or jittery signal generation
Slogsnat et al. An open-source hypertransport core
US6701490B1 (en) Cycle and phase accurate hardware-software coverification
US20100017656A1 (en) System on chip (SOC) device verification system using memory interface
US7882473B2 (en) Sequential equivalence checking for asynchronous verification

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JA, YEE;NELSON, BRADLEY S.;REEL/FRAME:017040/0026

Effective date: 20051014