DE602008004157D1 - Rekonfigurierbare logikzelle aus doppelgate-mosfet-transistoren - Google Patents

Rekonfigurierbare logikzelle aus doppelgate-mosfet-transistoren

Info

Publication number
DE602008004157D1
DE602008004157D1 DE602008004157T DE602008004157T DE602008004157D1 DE 602008004157 D1 DE602008004157 D1 DE 602008004157D1 DE 602008004157 T DE602008004157 T DE 602008004157T DE 602008004157 T DE602008004157 T DE 602008004157T DE 602008004157 D1 DE602008004157 D1 DE 602008004157D1
Authority
DE
Germany
Prior art keywords
mosfet transistors
reconfigurable logic
cell
dual gate
logic cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602008004157T
Other languages
English (en)
Inventor
Ian D O'connor
Ilham Hassoune
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Ecole Centrale de Lyon
Original Assignee
Centre National de la Recherche Scientifique CNRS
Ecole Centrale de Lyon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS, Ecole Centrale de Lyon filed Critical Centre National de la Recherche Scientifique CNRS
Publication of DE602008004157D1 publication Critical patent/DE602008004157D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/0813—Threshold logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1738—Controllable logic circuits using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE602008004157T 2007-07-13 2008-07-11 Rekonfigurierbare logikzelle aus doppelgate-mosfet-transistoren Active DE602008004157D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0756487A FR2918823B1 (fr) 2007-07-13 2007-07-13 Cellule logique reconfigurable a base de transistors mosfet double grille
PCT/FR2008/051309 WO2009013422A2 (fr) 2007-07-13 2008-07-11 Cellule logique reconfigurable a base de transistors mosfet double grille

Publications (1)

Publication Number Publication Date
DE602008004157D1 true DE602008004157D1 (de) 2011-02-03

Family

ID=39027947

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602008004157T Active DE602008004157D1 (de) 2007-07-13 2008-07-11 Rekonfigurierbare logikzelle aus doppelgate-mosfet-transistoren

Country Status (7)

Country Link
US (1) US7859308B2 (de)
EP (1) EP2171851B1 (de)
JP (1) JP5183737B2 (de)
AT (1) ATE492944T1 (de)
DE (1) DE602008004157D1 (de)
FR (1) FR2918823B1 (de)
WO (1) WO2009013422A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2953641B1 (fr) 2009-12-08 2012-02-10 S O I Tec Silicon On Insulator Tech Circuit de transistors homogenes sur seoi avec grille de controle arriere enterree sous la couche isolante
FR2953643B1 (fr) 2009-12-08 2012-07-27 Soitec Silicon On Insulator Cellule memoire flash sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante
FR2957193B1 (fr) 2010-03-03 2012-04-20 Soitec Silicon On Insulator Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante
US8508289B2 (en) 2009-12-08 2013-08-13 Soitec Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
FR2954023B1 (fr) 2009-12-14 2012-02-10 Lyon Ecole Centrale Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee
FR2955195B1 (fr) * 2010-01-14 2012-03-09 Soitec Silicon On Insulator Dispositif de comparaison de donnees dans une memoire adressable par contenu sur seoi
FR2955200B1 (fr) 2010-01-14 2012-07-20 Soitec Silicon On Insulator Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree
FR2955203B1 (fr) 2010-01-14 2012-03-23 Soitec Silicon On Insulator Cellule memoire dont le canal traverse une couche dielectrique enterree
FR2955204B1 (fr) 2010-01-14 2012-07-20 Soitec Silicon On Insulator Cellule memoire dram disposant d'un injecteur bipolaire vertical
FR2957186B1 (fr) 2010-03-08 2012-09-28 Soitec Silicon On Insulator Cellule memoire de type sram
FR2957449B1 (fr) 2010-03-11 2022-07-15 S O I Tec Silicon On Insulator Tech Micro-amplificateur de lecture pour memoire
FR2958441B1 (fr) 2010-04-02 2012-07-13 Soitec Silicon On Insulator Circuit pseudo-inverseur sur seoi
EP2378549A1 (de) 2010-04-06 2011-10-19 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung eines Halbleitersubstrats
EP2381470B1 (de) 2010-04-22 2012-08-22 Soitec Halbleiterbauelement mit einem Feldeffekttransistor in einer Silizium-auf-Isolator-Struktur
FR2967534A1 (fr) * 2010-11-15 2012-05-18 Centre Nat Rech Scient Porte logique dynamique programmable
RU2629698C1 (ru) * 2016-05-25 2017-08-31 Федеральное государственное учреждение "Федеральный научный центр Научно-исследовательский институт системных исследований Российской академии наук" (ФГУ ФНЦ НИИСИ РАН) Однотранзисторный логический вентиль И с архитектурой без перекрытия областей затвор-сток/исток

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0264334B1 (de) * 1986-10-16 1994-12-28 Fairchild Semiconductor Corporation Synchrone Array-Logikschaltung
US5402012A (en) * 1993-04-19 1995-03-28 Vlsi Technology, Inc. Sequentially clocked domino-logic cells
US5777491A (en) * 1995-03-31 1998-07-07 International Business Machines Corporation High-performance differential cascode voltage switch with pass gate logic elements
US6046606A (en) * 1998-01-21 2000-04-04 International Business Machines Corporation Soft error protected dynamic circuit
US6580293B1 (en) * 2001-12-14 2003-06-17 International Business Machines Corporation Body-contacted and double gate-contacted differential logic circuit and method of operation
JP2003318727A (ja) * 2002-04-18 2003-11-07 Toshiba Corp 半導体論理演算回路
US6717438B2 (en) * 2002-08-30 2004-04-06 Sun Microsystems, Inc. Clocked half-rail differential logic with single-rail logic
US7652330B1 (en) * 2003-07-03 2010-01-26 American Semiconductor, Inc. Independently-double-gated combinational logic
US7265589B2 (en) * 2005-06-28 2007-09-04 International Business Machines Corporation Independent gate control logic circuitry
US7382162B2 (en) * 2005-07-14 2008-06-03 International Business Machines Corporation High-density logic techniques with reduced-stack multi-gate field effect transistors
US7298176B2 (en) * 2005-08-16 2007-11-20 International Business Machines Corporation Dual-gate dynamic logic circuit with pre-charge keeper
US7592841B2 (en) * 2006-05-11 2009-09-22 Dsm Solutions, Inc. Circuit configurations having four terminal JFET devices

Also Published As

Publication number Publication date
FR2918823A1 (fr) 2009-01-16
JP2010533402A (ja) 2010-10-21
US7859308B2 (en) 2010-12-28
JP5183737B2 (ja) 2013-04-17
WO2009013422A2 (fr) 2009-01-29
EP2171851B1 (de) 2010-12-22
ATE492944T1 (de) 2011-01-15
US20100194430A1 (en) 2010-08-05
EP2171851A2 (de) 2010-04-07
FR2918823B1 (fr) 2009-10-16
WO2009013422A3 (fr) 2009-03-12

Similar Documents

Publication Publication Date Title
DE602008004157D1 (de) Rekonfigurierbare logikzelle aus doppelgate-mosfet-transistoren
TW200746313A (en) A tensile strained NMOS transistor using group III-N source/drain regions
WO2003075454A3 (en) Operational amplifier with increased common mode input range
WO2014078677A8 (en) Wide common mode range transmission gate
WO2008141098A3 (en) Dynamically configurable high speed interconnect using a nonlinear element
TW200707392A (en) A three-level driving shift register
DE602006017834D1 (de) Fet-transistornetzwerk auf basis von halbleitenden nanoröhrchen oder nanodrähten und entsprechende e
TW200501558A (en) Differential amplifier operable in wide range
TW200703905A (en) Logical circuit and single electron spin transistor
TW200727451A (en) Cascode circuit
Sharma et al. Low power 8-bit ALU design using full adder and multiplexer
WO2008134225A3 (en) Integrated circuit switching device, structure and method of manufacture
WO2011126471A3 (en) System and method for providing symmetric, efficient bi-directional power flow and power conditioning
WO2010099442A3 (en) Reconfigurable and reliable logic circuit elements that exploit nonlinearity and noise
TW200746620A (en) Limiter circuit
TW200608567A (en) High voltage tolerance output stage
DE602006015864D1 (de) Verfahren und anordnung für einen linearmischer
WO2004084411A8 (fr) Diviseur de frequence a taux de division variable
Jabeur et al. High performance 4: 1 multiplexer with ambipolar double-gate FETs
TW200627799A (en) Logic circuit combining exclusive or gate and exclusive nor gate
RU2011117657A (ru) Статическая запоминающая ячейка с двумя адресными входами
SG141293A1 (en) 2-transistor nonvolatile memory cell
Gadekar et al. Design of 16T full adder circuit using 6TXNOR gates
TW200633388A (en) A gate oxide protected I/O circuit
RU2475811C1 (ru) Полный сумматор