DE602006007695D1 - Prüfbare elektronische schaltung - Google Patents

Prüfbare elektronische schaltung

Info

Publication number
DE602006007695D1
DE602006007695D1 DE602006007695T DE602006007695T DE602006007695D1 DE 602006007695 D1 DE602006007695 D1 DE 602006007695D1 DE 602006007695 T DE602006007695 T DE 602006007695T DE 602006007695 T DE602006007695 T DE 602006007695T DE 602006007695 D1 DE602006007695 D1 DE 602006007695D1
Authority
DE
Germany
Prior art keywords
circuit
test
functional
clock
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006007695T
Other languages
English (en)
Inventor
Herve Fleury
Jean-Marc Yannou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602006007695D1 publication Critical patent/DE602006007695D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Cephalosporin Compounds (AREA)
DE602006007695T 2005-02-01 2006-01-31 Prüfbare elektronische schaltung Active DE602006007695D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05300077 2005-02-01
PCT/IB2006/050326 WO2006082555A1 (en) 2005-02-01 2006-01-31 Testable electronic circuit

Publications (1)

Publication Number Publication Date
DE602006007695D1 true DE602006007695D1 (de) 2009-08-20

Family

ID=36481279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006007695T Active DE602006007695D1 (de) 2005-02-01 2006-01-31 Prüfbare elektronische schaltung

Country Status (7)

Country Link
US (1) US7899641B2 (de)
EP (1) EP1875256B1 (de)
JP (1) JP2008528999A (de)
CN (1) CN101163978B (de)
AT (1) ATE436028T1 (de)
DE (1) DE602006007695D1 (de)
WO (1) WO2006082555A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8432181B2 (en) * 2008-07-25 2013-04-30 Thomson Licensing Method and apparatus for reconfigurable at-speed test clock generator
CN101762783B (zh) * 2010-01-18 2011-12-21 山东华芯半导体有限公司 一种片上测试电路有效误差信息的读出方法
US9354274B2 (en) * 2012-08-13 2016-05-31 Nanya Technology Corporation Circuit test system electric element memory control chip under different test modes
US9092333B2 (en) 2013-01-04 2015-07-28 International Business Machines Corporation Fault isolation with abstracted objects
FR3023027B1 (fr) * 2014-06-27 2016-07-29 St Microelectronics Crolles 2 Sas Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe
US9459317B2 (en) 2014-08-28 2016-10-04 Freescale Semiconductor, Inc. Mixed mode integrated circuit, method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit
US9607583B2 (en) 2014-09-05 2017-03-28 Nxp Usa, Inc. Display controller device having a debug interface
US20160163609A1 (en) * 2014-12-03 2016-06-09 Altera Corporation Methods and apparatus for testing auxiliary components in a multichip package
US10014899B2 (en) * 2016-07-15 2018-07-03 Texas Instruments Incorporated System and method for built-in self-test of electronic circuits

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2638281B2 (ja) * 1990-10-08 1997-08-06 日本電気株式会社 スキャンパス回路
US5606565A (en) * 1995-02-14 1997-02-25 Hughes Electronics Method of applying boundary test patterns
US6260165B1 (en) * 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
KR100499740B1 (ko) * 1996-12-13 2005-09-30 코닌클리케 필립스 일렉트로닉스 엔.브이. 제1및제2클록도메인을포함하는집적회로및그러한회로를테스트하는방법
CA2225879C (en) * 1997-12-29 2001-05-01 Jean-Francois Cote Clock skew management method and apparatus
US6393592B1 (en) * 1999-05-21 2002-05-21 Adaptec, Inc. Scan flop circuitry and methods for making the same
US6484280B1 (en) * 1999-09-30 2002-11-19 Agilent Technologies Inc. Scan path test support
US6763489B2 (en) * 2001-02-02 2004-07-13 Logicvision, Inc. Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description
US20030084390A1 (en) 2001-10-26 2003-05-01 Mentor Graphics Corporation At-speed test using on-chip controller
US7000164B2 (en) * 2002-01-30 2006-02-14 Sun Microsystems, Inc. Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops
US6861867B2 (en) * 2002-03-07 2005-03-01 Lightspeed Semiconductor Corporation Method and apparatus for built-in self-test of logic circuits with multiple clock domains
KR20050105221A (ko) * 2003-02-18 2005-11-03 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 전자 회로, 테스트 시스템, 집적 회로 및 전자 회로 테스트방법
TWI235841B (en) * 2003-07-02 2005-07-11 Realtek Semiconductor Corp Multi-clock domain logic device for performing scan test with single scan clock and method thereof

Also Published As

Publication number Publication date
EP1875256B1 (de) 2009-07-08
WO2006082555A1 (en) 2006-08-10
US20080133167A1 (en) 2008-06-05
US7899641B2 (en) 2011-03-01
CN101163978B (zh) 2010-08-25
EP1875256A1 (de) 2008-01-09
ATE436028T1 (de) 2009-07-15
JP2008528999A (ja) 2008-07-31
CN101163978A (zh) 2008-04-16

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Legal Events

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