DE602006001076D1 - Taktdatenrückgewinnungsschaltung mit Sperren eines Schaltungskreises - Google Patents
Taktdatenrückgewinnungsschaltung mit Sperren eines SchaltungskreisesInfo
- Publication number
- DE602006001076D1 DE602006001076D1 DE602006001076T DE602006001076T DE602006001076D1 DE 602006001076 D1 DE602006001076 D1 DE 602006001076D1 DE 602006001076 T DE602006001076 T DE 602006001076T DE 602006001076 T DE602006001076 T DE 602006001076T DE 602006001076 D1 DE602006001076 D1 DE 602006001076D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- locking
- data recovery
- clock data
- recovery circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000011084 recovery Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Memory System (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/093,554 US7681063B2 (en) | 2005-03-30 | 2005-03-30 | Clock data recovery circuit with circuit loop disablement |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006001076D1 true DE602006001076D1 (de) | 2008-06-19 |
Family
ID=37083166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006001076T Active DE602006001076D1 (de) | 2005-03-30 | 2006-03-27 | Taktdatenrückgewinnungsschaltung mit Sperren eines Schaltungskreises |
Country Status (6)
Country | Link |
---|---|
US (1) | US7681063B2 (de) |
EP (1) | EP1729418B1 (de) |
JP (1) | JP4290706B2 (de) |
KR (1) | KR100776103B1 (de) |
CN (1) | CN1855295B (de) |
DE (1) | DE602006001076D1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070016835A1 (en) * | 2005-07-12 | 2007-01-18 | Integrated Device Technology, Inc. | Method and apparatus for parameter adjustment, testing, and configuration |
DE102008008051A1 (de) * | 2008-02-08 | 2009-08-20 | Qimonda Ag | Speichermodul und Betriebsverfahren für ein Speichermodul |
US8331514B2 (en) | 2010-04-16 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Digital second-order CDR circuits |
US8995597B2 (en) | 2010-04-16 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Digital second-order CDR circuits |
JP2012109931A (ja) * | 2010-10-25 | 2012-06-07 | Ricoh Co Ltd | オーバーサンプリング回路及びそれを用いたシリアル通信装置及びシリアル通信方法 |
US8564352B2 (en) | 2012-02-10 | 2013-10-22 | International Business Machines Corporation | High-resolution phase interpolators |
US9444442B2 (en) | 2013-03-06 | 2016-09-13 | Rambus Inc. | Open-loop correction of duty-cycle error and quadrature phase error |
US9325489B2 (en) * | 2013-12-19 | 2016-04-26 | Xilinx, Inc. | Data receivers and methods of implementing data receivers in an integrated circuit |
WO2015161431A1 (zh) * | 2014-04-22 | 2015-10-29 | 京微雅格(北京)科技有限公司 | Lvds数据恢复方法及电路 |
KR102599059B1 (ko) * | 2018-10-11 | 2023-11-08 | 삼성디스플레이 주식회사 | 트랜지션 검출기 및 이를 포함하는 클록 데이터 복원기 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4821297A (en) * | 1987-11-19 | 1989-04-11 | American Telephone And Telegraph Company, At&T Bell Laboratories | Digital phase locked loop clock recovery scheme |
KR950008462B1 (ko) * | 1992-04-22 | 1995-07-31 | 재단법인 한국전자통신연구소 | 디지틀 비트 동기 장치 |
US5463351A (en) * | 1994-09-29 | 1995-10-31 | Motorola, Inc. | Nested digital phase lock loop |
US5850422A (en) | 1995-07-21 | 1998-12-15 | Symbios, Inc. | Apparatus and method for recovering a clock signal which is embedded in an incoming data stream |
US6055225A (en) * | 1997-06-02 | 2000-04-25 | Hewlett-Packard Company | Ring architecture for quad port bypass circuits |
US6266799B1 (en) * | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
US6643346B1 (en) | 1999-02-23 | 2003-11-04 | Rockwell Scientific Company Llc | Frequency detection circuit for clock recovery |
WO2001006696A1 (en) * | 1999-07-16 | 2001-01-25 | Conexant Systems, Inc. | Apparatus and method for servo-controlled self-centering phase detector |
US7099424B1 (en) * | 2001-08-28 | 2006-08-29 | Rambus Inc. | Clock data recovery with selectable phase control |
US6750675B2 (en) * | 2001-09-17 | 2004-06-15 | Altera Corporation | Programmable logic devices with multi-standard byte synchronization and channel alignment for communication |
US7020227B1 (en) * | 2002-05-31 | 2006-03-28 | Acard Technology Corporation | Method and apparatus for high-speed clock data recovery using low-speed circuits |
US7142623B2 (en) * | 2002-05-31 | 2006-11-28 | International Business Machines Corporation | On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit |
US7138837B2 (en) * | 2003-01-21 | 2006-11-21 | Altera Corporation | Digital phase locked loop circuitry and methods |
US7076377B2 (en) * | 2003-02-11 | 2006-07-11 | Rambus Inc. | Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit |
JP4335586B2 (ja) * | 2003-06-11 | 2009-09-30 | Necエレクトロニクス株式会社 | クロックアンドデータリカバリ回路 |
US7817767B2 (en) * | 2004-12-23 | 2010-10-19 | Rambus Inc. | Processor-controlled clock-data recovery |
US7532697B1 (en) * | 2005-01-27 | 2009-05-12 | Net Logic Microsystems, Inc. | Methods and apparatus for clock and data recovery using a single source |
-
2005
- 2005-03-30 US US11/093,554 patent/US7681063B2/en not_active Expired - Fee Related
-
2006
- 2006-03-27 EP EP06006264A patent/EP1729418B1/de not_active Expired - Fee Related
- 2006-03-27 DE DE602006001076T patent/DE602006001076D1/de active Active
- 2006-03-30 JP JP2006094106A patent/JP4290706B2/ja not_active Expired - Fee Related
- 2006-03-30 CN CN2006100840156A patent/CN1855295B/zh not_active Expired - Fee Related
- 2006-03-30 KR KR1020060029150A patent/KR100776103B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP1729418A3 (de) | 2007-01-03 |
EP1729418B1 (de) | 2008-05-07 |
KR100776103B1 (ko) | 2007-11-15 |
KR20060105611A (ko) | 2006-10-11 |
US20060227914A1 (en) | 2006-10-12 |
EP1729418A2 (de) | 2006-12-06 |
US7681063B2 (en) | 2010-03-16 |
CN1855295A (zh) | 2006-11-01 |
JP2006311530A (ja) | 2006-11-09 |
JP4290706B2 (ja) | 2009-07-08 |
CN1855295B (zh) | 2010-05-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602006001076D1 (de) | Taktdatenrückgewinnungsschaltung mit Sperren eines Schaltungskreises | |
NO345041B1 (no) | Antenneutsparing i et nedhulls rørelement | |
DE602005010242D1 (de) | Taktgeber mit weitem bereich | |
DK2036062T3 (da) | Elektronisk informationstavle | |
DE602005022402D1 (de) | Elektronische Uhr mit Kompassfunktion | |
DE602006015405D1 (de) | Inkrementelle Assoziation von Metadaten zu Produktionsdaten | |
IL183194A0 (en) | Latch circuit including a data retention latch | |
DK1882343T3 (da) | Forbedring af fejlrobustheden under anvendelse af båndbiblioteksoplysningsinformation | |
EP1920352A4 (de) | Elektonischer datenschnappschussgenerator | |
TWI369115B (en) | Signal interleaving for serial clock and data recovery | |
DE602007013504D1 (de) | Phasenregeloszillator | |
DE602005008353D1 (de) | Dekodierung eines CQI | |
DE602007007007D1 (de) | Einschätzung des Jitters eines Taktsignals | |
ITMI20062007A1 (it) | Serratura elettronica per serramenti | |
DE602007012519D1 (de) | Integrierte Schaltung mit beschränktem Datenzugang | |
DE602005024573D1 (de) | Taktregenerierungsschaltung | |
SG120297A1 (en) | A clock and data recovery circuit | |
DE602008001176D1 (de) | Taktwiederherstellungsvorrichtung | |
DE602005025857D1 (de) | P-Domino Datenregister | |
FR2900456B1 (fr) | Raccord a double verrouillage | |
SE0501484L (sv) | Flerpunktslås | |
DE602006005318D1 (de) | Elektronische Komponente | |
DE112006001105A5 (de) | Magnetschloss | |
DE602005019558D1 (de) | Symboltakt-mehrdeutigkeitskorrektur | |
FR2908394B1 (fr) | Frette a verrouillage securise |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: LANTIQ DEUTSCHLAND GMBH, 85579 NEUBIBERG, DE |