DE602005024573D1 - Taktregenerierungsschaltung - Google Patents

Taktregenerierungsschaltung

Info

Publication number
DE602005024573D1
DE602005024573D1 DE602005024573T DE602005024573T DE602005024573D1 DE 602005024573 D1 DE602005024573 D1 DE 602005024573D1 DE 602005024573 T DE602005024573 T DE 602005024573T DE 602005024573 T DE602005024573 T DE 602005024573T DE 602005024573 D1 DE602005024573 D1 DE 602005024573D1
Authority
DE
Germany
Prior art keywords
regeneration circuit
clock regeneration
clock
circuit
regeneration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005024573T
Other languages
English (en)
Inventor
Masahiro Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE602005024573D1 publication Critical patent/DE602005024573D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
DE602005024573T 2004-08-30 2005-08-15 Taktregenerierungsschaltung Active DE602005024573D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004250067 2004-08-30
PCT/JP2005/014914 WO2006025212A1 (ja) 2004-08-30 2005-08-15 クロック再生回路

Publications (1)

Publication Number Publication Date
DE602005024573D1 true DE602005024573D1 (de) 2010-12-16

Family

ID=35999870

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005024573T Active DE602005024573D1 (de) 2004-08-30 2005-08-15 Taktregenerierungsschaltung

Country Status (6)

Country Link
US (1) US7924962B2 (de)
EP (1) EP1786165B1 (de)
JP (1) JP4389934B2 (de)
CN (1) CN101002449B (de)
DE (1) DE602005024573D1 (de)
WO (1) WO2006025212A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1976109A1 (de) * 2007-03-31 2008-10-01 Sony Deutschland Gmbh Demodulator, Verfahren und Empfänger für Demodulation
EP2375603B1 (de) * 2010-02-05 2018-05-23 Xieon Networks S.à r.l. Taktwiederherstellungsverfahren und Taktwiederherstellungsanordung für Multiplex-Empfänger mit kohärenter Polarisation
US9001943B2 (en) * 2013-03-14 2015-04-07 Altera Corporation Digital equalizer adaptation using on-die instrument
US9231751B1 (en) * 2014-09-18 2016-01-05 Realtek Semiconductor Corporation Clock-data recovery circuit and method thereof
CN111869157B (zh) * 2018-11-08 2022-04-22 华为技术有限公司 用于数据传输系统中的定时恢复装置和定时恢复方法
US11038549B1 (en) * 2020-06-08 2021-06-15 Ciena Corporation Receiver noise loading for control loop stability
US11736144B2 (en) * 2020-11-12 2023-08-22 Texas Instruments Incorporated Decomposed real-imaginary equalizer

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468786A (en) * 1982-09-21 1984-08-28 Harris Corporation Nonlinear equalizer for correcting intersymbol interference in a digital data transmission system
JPS6052147A (ja) * 1983-09-01 1985-03-25 Nec Corp タイミング同期方式
JPS6474830A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Automatic amplitude equalization circuit
EP0671829B1 (de) * 1994-03-11 2006-06-28 Fujitsu Limited Schaltungsanordnung zur Taktrückgewinnung
JPH09130443A (ja) * 1995-10-31 1997-05-16 Toshiba Corp ディジタル復調装置
JP3130794B2 (ja) * 1996-05-27 2001-01-31 日本電気株式会社 復調器
JP3404228B2 (ja) * 1996-09-10 2003-05-06 富士通株式会社 クロック位相検出回路
KR100241890B1 (ko) * 1997-01-10 2000-03-02 윤종용 디지털 통신 시스템에서 간섭 제거 회로
JPH1174942A (ja) * 1997-08-29 1999-03-16 Fujitsu Ltd 無線受信装置
JPH11331300A (ja) 1998-05-19 1999-11-30 Nec Corp 復調装置
JP2000270038A (ja) 1999-03-15 2000-09-29 Nec Corp クロック同期回路およびその同期方法

Also Published As

Publication number Publication date
WO2006025212A1 (ja) 2006-03-09
CN101002449B (zh) 2010-06-09
EP1786165A1 (de) 2007-05-16
EP1786165B1 (de) 2010-11-03
US7924962B2 (en) 2011-04-12
JPWO2006025212A1 (ja) 2008-05-08
JP4389934B2 (ja) 2009-12-24
EP1786165A4 (de) 2007-11-07
US20070253515A1 (en) 2007-11-01
CN101002449A (zh) 2007-07-18

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