DE602005025857D1 - P-Domino Datenregister - Google Patents

P-Domino Datenregister

Info

Publication number
DE602005025857D1
DE602005025857D1 DE602005025857T DE602005025857T DE602005025857D1 DE 602005025857 D1 DE602005025857 D1 DE 602005025857D1 DE 602005025857 T DE602005025857 T DE 602005025857T DE 602005025857 T DE602005025857 T DE 602005025857T DE 602005025857 D1 DE602005025857 D1 DE 602005025857D1
Authority
DE
Germany
Prior art keywords
data register
domino data
domino
register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005025857T
Other languages
English (en)
Inventor
James R Lundberg
Raymond A Bertram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/023,145 external-priority patent/US7187209B2/en
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of DE602005025857D1 publication Critical patent/DE602005025857D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE602005025857T 2004-12-27 2005-11-15 P-Domino Datenregister Active DE602005025857D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/023,145 US7187209B2 (en) 2003-08-13 2004-12-27 Non-inverting domino register
US11/251,384 US7187210B2 (en) 2003-08-13 2005-10-14 P-domino register

Publications (1)

Publication Number Publication Date
DE602005025857D1 true DE602005025857D1 (de) 2011-02-24

Family

ID=36084236

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005025857T Active DE602005025857D1 (de) 2004-12-27 2005-11-15 P-Domino Datenregister

Country Status (5)

Country Link
US (1) US7187210B2 (de)
EP (1) EP1732226B1 (de)
CN (1) CN100568734C (de)
DE (1) DE602005025857D1 (de)
ES (1) ES2359638T3 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7317339B1 (en) * 2006-06-16 2008-01-08 Via Technologies, Inc. N-domino register with accelerated non-discharge path
US7382161B2 (en) * 2006-08-11 2008-06-03 Via Technologies, Inc. Accelerated P-channel dynamic register
US7990180B2 (en) * 2009-09-09 2011-08-02 Via Technologies, Inc. Fast dynamic register
US8860463B1 (en) 2013-04-24 2014-10-14 Via Technologies, Inc. Fast dynamic register with transparent latch
US10581410B2 (en) * 2015-09-10 2020-03-03 Samsung Electronics Co., Ltd High speed domino-based flip flop

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075386A (en) * 1990-04-12 1991-12-24 Eastman Kodak Company Cross-linkable hot-melt adhesive and method of producing same
US5889979A (en) * 1996-05-24 1999-03-30 Hewlett-Packard, Co. Transparent data-triggered pipeline latch
US5926038A (en) * 1997-11-10 1999-07-20 The United States Of America As Represented By The Secretary Of The Navy Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication
US6265899B1 (en) * 1999-06-04 2001-07-24 S3 Incorporated Single rail domino logic for four-phase clocking scheme
US6191618B1 (en) * 1999-07-23 2001-02-20 Intel Corporation Contention-free, low clock load domino circuit topology
US6560737B1 (en) * 2000-02-16 2003-05-06 Hewlett-Packard Development Company, L.P. Method for adding scan controllability and observability to domino CMOS with low area and delay overhead
US6496038B1 (en) * 2000-06-30 2002-12-17 Intel Corporation Pulsed circuit topology including a pulsed, domino flip-flop
US6877822B2 (en) 2000-11-21 2005-04-12 Continental Teves Ag & Co., Ohg Hydraulic unit for anti-slip regulated braking systems
US6498514B2 (en) * 2001-04-30 2002-12-24 Intel Corporation Domino circuit
US6956406B2 (en) * 2001-07-02 2005-10-18 Intrinsity, Inc. Static storage element for dynamic logic
GB0121013D0 (en) * 2001-08-30 2001-10-24 Micron Technology Inc Combined dynamic logic gate and level shifter and method employing same
US6628143B2 (en) * 2001-09-26 2003-09-30 Intel Corporation Full-swing source-follower leakage tolerant dynamic logic
US6650145B2 (en) * 2002-04-04 2003-11-18 International Business Machines Corporation Circuits and systems for limited switch dynamic logic
US7034578B2 (en) * 2003-04-28 2006-04-25 Via Technologies, Inc. N-domino output latch with accelerated evaluate path
US7212039B2 (en) * 2003-08-27 2007-05-01 Via Technologies, Inc. Dynamic logic register
US20050110522A1 (en) * 2003-11-21 2005-05-26 Hoekstra George P. Multistage dynamic domino circuit with internally generated delay reset clock

Also Published As

Publication number Publication date
CN100568734C (zh) 2009-12-09
EP1732226A3 (de) 2009-03-04
EP1732226A2 (de) 2006-12-13
CN1929306A (zh) 2007-03-14
US7187210B2 (en) 2007-03-06
EP1732226B1 (de) 2011-01-12
ES2359638T3 (es) 2011-05-25
US20060038589A1 (en) 2006-02-23

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