DE602004010285D1 - Statisches latch - Google Patents

Statisches latch

Info

Publication number
DE602004010285D1
DE602004010285D1 DE602004010285T DE602004010285T DE602004010285D1 DE 602004010285 D1 DE602004010285 D1 DE 602004010285D1 DE 602004010285 T DE602004010285 T DE 602004010285T DE 602004010285 T DE602004010285 T DE 602004010285T DE 602004010285 D1 DE602004010285 D1 DE 602004010285D1
Authority
DE
Germany
Prior art keywords
static latch
latch
static
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004010285T
Other languages
English (en)
Other versions
DE602004010285T2 (de
Inventor
Paul Wielage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602004010285D1 publication Critical patent/DE602004010285D1/de
Application granted granted Critical
Publication of DE602004010285T2 publication Critical patent/DE602004010285T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
DE602004010285T 2003-09-03 2004-08-26 Statisches latch Active DE602004010285T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03103273 2003-09-03
EP03103273 2003-09-03
PCT/IB2004/002807 WO2005022746A1 (en) 2003-09-03 2004-08-26 A static latch

Publications (2)

Publication Number Publication Date
DE602004010285D1 true DE602004010285D1 (de) 2008-01-03
DE602004010285T2 DE602004010285T2 (de) 2008-09-25

Family

ID=34259240

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004010285T Active DE602004010285T2 (de) 2003-09-03 2004-08-26 Statisches latch

Country Status (8)

Country Link
US (1) US20070001727A1 (de)
EP (1) EP1665530B1 (de)
JP (1) JP2007504734A (de)
KR (1) KR20060131727A (de)
CN (1) CN100576742C (de)
DE (1) DE602004010285T2 (de)
TW (1) TW200520385A (de)
WO (1) WO2005022746A1 (de)

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US7839168B2 (en) * 2006-12-12 2010-11-23 Nxp B.V. Circuit with parallel functional circuits with multi-phase control inputs
RU2405246C2 (ru) * 2008-04-15 2010-11-27 Институт проблем информатики Российской академии наук (ИПИ РАН) Самосинхронный триггер с однофазным информационным входом
US8686778B2 (en) * 2009-08-24 2014-04-01 Oracle America, Inc. Integrated pulse-control and enable latch circuit
CN102800363A (zh) * 2012-09-05 2012-11-28 苏州硅智源微电子有限公司 一种双向移位寄存器
JP6273112B2 (ja) * 2012-09-11 2018-01-31 株式会社半導体エネルギー研究所 フリップフロップ回路および半導体装置
KR101408196B1 (ko) * 2012-12-21 2014-06-16 충북대학교 산학협력단 정적 펄스 플립플롭을 이용한 저전력/저면적 쉬프트 레지스터
KR102192543B1 (ko) * 2014-04-04 2020-12-18 에스케이하이닉스 주식회사 신호 전달회로 및 그의 동작방법
CN104360781B (zh) * 2014-11-12 2017-10-03 京东方科技集团股份有限公司 触控电极的驱动单元、驱动电路、触控面板及驱动方法
US9584121B2 (en) * 2015-06-10 2017-02-28 Qualcomm Incorporated Compact design of scan latch
US9614502B2 (en) * 2015-08-04 2017-04-04 Qualcomm Incorporated Accurate sample latch offset compensation scheme
CN107317569A (zh) * 2017-06-16 2017-11-03 上海华虹宏力半导体制造有限公司 数据触发器装置
US10529412B1 (en) * 2019-04-09 2020-01-07 Micron Technology, Inc. Output buffer circuit with non-target ODT function

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US4833347A (en) * 1986-02-28 1989-05-23 Honeywell, Inc. Charge disturbance resistant logic circuits utilizing true and complement input control circuits
US5281865A (en) * 1990-11-28 1994-01-25 Hitachi, Ltd. Flip-flop circuit
JP2871087B2 (ja) * 1990-11-30 1999-03-17 日本電気株式会社 フリップフロップ回路
US5455528A (en) * 1993-11-15 1995-10-03 Intergraph Corporation CMOS circuit for implementing Boolean functions
JPH07154213A (ja) * 1993-11-30 1995-06-16 Toshiba Corp 半導体集積回路
US5497115A (en) * 1994-04-29 1996-03-05 Mosaid Technologies Incorporated Flip-flop circuit having low standby power for driving synchronous dynamic random access memory
US5552737A (en) * 1994-07-11 1996-09-03 International Business Machines Corporation Scannable master slave latch actuated by single phase clock
US5508648A (en) * 1994-08-01 1996-04-16 Intel Corporation Differential latch circuit
US5650735A (en) * 1995-03-24 1997-07-22 Texas Instruments Incorporated Low power, high performance latching interfaces for converting dynamic inputs into static outputs
JPH0993118A (ja) * 1995-09-22 1997-04-04 Kawasaki Steel Corp パストランジスタ論理回路
JPH09232920A (ja) * 1996-02-28 1997-09-05 Nec Ic Microcomput Syst Ltd フリップフロップ回路
US5760627A (en) * 1996-03-12 1998-06-02 International Business Machines Corporation Low power CMOS latch
JP3241619B2 (ja) * 1996-12-25 2001-12-25 シャープ株式会社 Ｃｍｏｓ論理回路
JP3544096B2 (ja) * 1997-03-26 2004-07-21 東京大学長 半導体集積回路装置
US6046608A (en) * 1997-12-08 2000-04-04 Intel Corporation Differential precharge circuit
US5986490A (en) * 1997-12-18 1999-11-16 Advanced Micro Devices, Inc. Amplifier-based flip-flop elements
JPH11243326A (ja) * 1997-12-24 1999-09-07 Nec Corp スタティックラッチ回路及びスタティック論理回路
KR100275948B1 (ko) * 1998-04-14 2000-12-15 김영환 차동모드낸드/노어게이트
US6084455A (en) * 1998-08-13 2000-07-04 Digital Equipment Corporation High-speed CMOS latch
AU3754100A (en) * 1999-03-19 2000-10-09 Moscape, Inc. System and method for performing assertion-based analysis of circuit designs
US20020070782A1 (en) * 1999-12-13 2002-06-13 Afghahi Morteza Cyrus High speed flip-flop
US6459317B1 (en) * 1999-12-22 2002-10-01 Texas Instruments Incorporated Sense amplifier flip-flop
US6348824B1 (en) * 2000-07-28 2002-02-19 Fujitsu, Limited High speed static latch
US6304122B1 (en) * 2000-08-17 2001-10-16 International Business Machines Corporation Low power LSSD flip flops and a flushable single clock splitter for flip flops
JP3727838B2 (ja) * 2000-09-27 2005-12-21 株式会社東芝 半導体集積回路
US6433601B1 (en) * 2000-12-15 2002-08-13 Koninklijke Philips Electronics N.V. Pulsed D-Flip-Flop using differential cascode switch
JP2002261601A (ja) * 2001-03-06 2002-09-13 Toshiba Corp 同期回路および半導体集積回路装置
US6507228B2 (en) * 2001-05-03 2003-01-14 International Business Machines Corporation Method and apparatus for latching a clocked data signal
JP3673230B2 (ja) * 2002-03-06 2005-07-20 日本電信電話株式会社 フリップフロップ回路
US6455336B1 (en) * 2001-08-27 2002-09-24 International Business Machines Corporation Power reduction method and design technique for burn-in
JP2003168735A (ja) * 2001-11-30 2003-06-13 Hitachi Ltd 半導体集積回路装置
US6580293B1 (en) * 2001-12-14 2003-06-17 International Business Machines Corporation Body-contacted and double gate-contacted differential logic circuit and method of operation
US6762957B2 (en) * 2001-12-20 2004-07-13 Intel Corporation Low clock swing latch for dual-supply voltage design
US6563357B1 (en) * 2001-12-20 2003-05-13 Intel Corporation Level converting latch
US6724221B2 (en) * 2002-03-28 2004-04-20 International Business Machines Corporation Circuitry having exclusive-OR and latch function, and method therefor
US6741101B1 (en) * 2002-10-15 2004-05-25 Sun Microsystems, Inc. Method for clock control of clocked half-rail differential logic with single-rail logic

Also Published As

Publication number Publication date
EP1665530A1 (de) 2006-06-07
TW200520385A (en) 2005-06-16
WO2005022746A1 (en) 2005-03-10
KR20060131727A (ko) 2006-12-20
JP2007504734A (ja) 2007-03-01
US20070001727A1 (en) 2007-01-04
CN1846351A (zh) 2006-10-11
CN100576742C (zh) 2009-12-30
DE602004010285T2 (de) 2008-09-25
EP1665530B1 (de) 2007-11-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition