DE60126207D1 - Halbleitervorrichtung und verfahren zu deren herstellung - Google Patents

Halbleitervorrichtung und verfahren zu deren herstellung

Info

Publication number
DE60126207D1
DE60126207D1 DE60126207T DE60126207T DE60126207D1 DE 60126207 D1 DE60126207 D1 DE 60126207D1 DE 60126207 T DE60126207 T DE 60126207T DE 60126207 T DE60126207 T DE 60126207T DE 60126207 D1 DE60126207 D1 DE 60126207D1
Authority
DE
Germany
Prior art keywords
passage
metal
organic material
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60126207T
Other languages
English (en)
Other versions
DE60126207T2 (de
Inventor
M Meijer
A Mutsaers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=8171227&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60126207(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE60126207D1 publication Critical patent/DE60126207D1/de
Application granted granted Critical
Publication of DE60126207T2 publication Critical patent/DE60126207T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE60126207T 2000-03-20 2001-02-23 Halbleitervorrichtung und verfahren zu deren herstellung Expired - Lifetime DE60126207T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP00201006 2000-03-20
EP00201006 2000-03-20
PCT/EP2001/002134 WO2001071801A1 (en) 2000-03-20 2001-02-23 Semiconductor device and method of manufacturing same

Publications (2)

Publication Number Publication Date
DE60126207D1 true DE60126207D1 (de) 2007-03-15
DE60126207T2 DE60126207T2 (de) 2007-11-15

Family

ID=8171227

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60126207T Expired - Lifetime DE60126207T2 (de) 2000-03-20 2001-02-23 Halbleitervorrichtung und verfahren zu deren herstellung

Country Status (8)

Country Link
US (2) US6613668B2 (de)
EP (1) EP1183725B1 (de)
JP (1) JP2003528467A (de)
KR (1) KR100749970B1 (de)
AT (1) ATE352869T1 (de)
DE (1) DE60126207T2 (de)
TW (1) TWI228787B (de)
WO (1) WO2001071801A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003528467A (ja) * 2000-03-20 2003-09-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体装置およびその製造方法
US20030155657A1 (en) 2002-02-14 2003-08-21 Nec Electronics Corporation Manufacturing method of semiconductor device
US6751785B1 (en) * 2002-03-12 2004-06-15 Ubitech, Inc. System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity
TWI288443B (en) * 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
US6740956B1 (en) * 2002-08-15 2004-05-25 National Semiconductor Corporation Metal trace with reduced RF impedance resulting from the skin effect
US6853079B1 (en) 2002-08-15 2005-02-08 National Semiconductor Corporation Conductive trace with reduced RF impedance resulting from the skin effect
US6703710B1 (en) 2002-08-15 2004-03-09 National Semiconductor Corporation Dual damascene metal trace with reduced RF impedance resulting from the skin effect
US6864581B1 (en) 2002-08-15 2005-03-08 National Semiconductor Corporation Etched metal trace with reduced RF impendance resulting from the skin effect
US20040222527A1 (en) * 2003-05-06 2004-11-11 Dostalik William W. Dual damascene pattern liner
WO2005041280A1 (en) * 2003-10-28 2005-05-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP2005167081A (ja) 2003-12-04 2005-06-23 Renesas Technology Corp 半導体装置およびその製造方法
US7341935B2 (en) * 2004-06-25 2008-03-11 Taiwan Semiconductor Manufacturing Co., Ltd. Alternative interconnect structure for semiconductor devices
TWI462179B (zh) * 2006-09-28 2014-11-21 Tokyo Electron Ltd 用以形成氧化矽膜之成膜方法與裝置
US8298628B2 (en) 2008-06-02 2012-10-30 Air Products And Chemicals, Inc. Low temperature deposition of silicon-containing films
KR101266135B1 (ko) * 2008-06-03 2013-05-27 도쿄엘렉트론가부시키가이샤 실리콘 함유 막의 저온 증착
CN102376633A (zh) * 2010-08-26 2012-03-14 中国科学院微电子研究所 一种半导体结构及其制造方法
US10930548B2 (en) * 2019-01-17 2021-02-23 Micron Technology, Inc. Methods of forming an apparatus for making semiconductor dieves

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
JPH10284600A (ja) 1997-03-31 1998-10-23 Sony Corp 半導体装置及びその製造方法
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
US5904565A (en) 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6025264A (en) * 1998-02-09 2000-02-15 United Microelectronics Corp. Fabricating method of a barrier layer
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2003528467A (ja) * 2000-03-20 2003-09-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体装置およびその製造方法
TW486801B (en) * 2000-04-07 2002-05-11 Taiwan Semiconductor Mfg Method of fabricating dual damascene structure

Also Published As

Publication number Publication date
JP2003528467A (ja) 2003-09-24
US6667236B2 (en) 2003-12-23
US20010023121A1 (en) 2001-09-20
WO2001071801A1 (en) 2001-09-27
KR20020005750A (ko) 2002-01-17
US6613668B2 (en) 2003-09-02
TWI228787B (en) 2005-03-01
ATE352869T1 (de) 2007-02-15
EP1183725A1 (de) 2002-03-06
KR100749970B1 (ko) 2007-08-16
DE60126207T2 (de) 2007-11-15
EP1183725B1 (de) 2007-01-24
US20030211737A1 (en) 2003-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN