DE60045734D1 - Verwendung eines isolierenden Abstandshalters zur Verhinderung von Schwellenspannung Roll-off in schmalen Bauelementen - Google Patents

Verwendung eines isolierenden Abstandshalters zur Verhinderung von Schwellenspannung Roll-off in schmalen Bauelementen

Info

Publication number
DE60045734D1
DE60045734D1 DE60045734T DE60045734T DE60045734D1 DE 60045734 D1 DE60045734 D1 DE 60045734D1 DE 60045734 T DE60045734 T DE 60045734T DE 60045734 T DE60045734 T DE 60045734T DE 60045734 D1 DE60045734 D1 DE 60045734D1
Authority
DE
Germany
Prior art keywords
threshold voltage
insulating spacer
voltage roll
narrow components
prevent threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60045734T
Other languages
English (en)
Inventor
Tammy Zheng
Faran Nouri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60045734D1 publication Critical patent/DE60045734D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE60045734T 1999-11-02 2000-10-26 Verwendung eines isolierenden Abstandshalters zur Verhinderung von Schwellenspannung Roll-off in schmalen Bauelementen Expired - Lifetime DE60045734D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/432,666 US6251747B1 (en) 1999-11-02 1999-11-02 Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices
PCT/US2000/029466 WO2001033626A1 (en) 1999-11-02 2000-10-26 Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices

Publications (1)

Publication Number Publication Date
DE60045734D1 true DE60045734D1 (de) 2011-04-28

Family

ID=23717108

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60045734T Expired - Lifetime DE60045734D1 (de) 1999-11-02 2000-10-26 Verwendung eines isolierenden Abstandshalters zur Verhinderung von Schwellenspannung Roll-off in schmalen Bauelementen

Country Status (7)

Country Link
US (1) US6251747B1 (de)
EP (1) EP1145304B1 (de)
JP (1) JP2003513469A (de)
KR (2) KR100707535B1 (de)
CN (1) CN1199256C (de)
DE (1) DE60045734D1 (de)
WO (1) WO2001033626A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492238B1 (en) 2001-06-22 2002-12-10 International Business Machines Corporation Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit
US6566225B2 (en) * 2001-08-06 2003-05-20 Macronix International Co., Ltd. Formation method of shallow trench isolation
US6661044B2 (en) * 2001-10-22 2003-12-09 Winbond Electronics Corp. Method of manufacturing MOSEFT and structure thereof
US20050135759A1 (en) * 2003-12-22 2005-06-23 Xingwu Wang Optical fiber assembly
US6541321B1 (en) * 2002-05-14 2003-04-01 Advanced Micro Devices, Inc. Method of making transistors with gate insulation layers of differing thickness
US6828211B2 (en) * 2002-10-01 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
KR100921329B1 (ko) * 2002-12-20 2009-10-13 매그나칩 반도체 유한회사 반도체 소자의 소자 분리막 형성 방법
SG121754A1 (en) * 2003-01-24 2006-05-26 Systems On Silicon Mfg Company Method of forming shallow trench isolation structures
KR100524809B1 (ko) 2003-12-19 2005-11-01 주식회사 하이닉스반도체 반도체 소자의 이중게이트 절연막 형성방법
US7037792B2 (en) * 2004-06-25 2006-05-02 Promos Technologies, Inc. Formation of removable shroud by anisotropic plasma etch
KR100753155B1 (ko) * 2006-05-09 2007-08-30 삼성전자주식회사 반도체 소자 및 그 형성 방법
US8110890B2 (en) * 2007-06-05 2012-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device isolation structure
KR100901822B1 (ko) * 2007-09-11 2009-06-09 주식회사 실트론 질화갈륨 성장용 기판 및 질화갈륨 기판 제조 방법
US8765491B2 (en) 2010-10-28 2014-07-01 International Business Machines Corporation Shallow trench isolation recess repair using spacer formation process
US8916950B2 (en) 2011-10-18 2014-12-23 International Business Machines Corporation Shallow trench isolation structure having a nitride plug
CN115497869B (zh) * 2022-11-17 2023-04-18 合肥新晶集成电路有限公司 半导体结构的制备方法及半导体结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654120A (en) 1985-10-31 1987-03-31 International Business Machines Corporation Method of making a planar trench semiconductor structure
US5433794A (en) 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
JPH07183409A (ja) * 1993-12-24 1995-07-21 Seiko Epson Corp 半導体装置とその製造方法
US5521422A (en) * 1994-12-02 1996-05-28 International Business Machines Corporation Corner protected shallow trench isolation device
US5882982A (en) 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
TW351849B (en) * 1997-09-11 1999-02-01 United Microelectronics Corp Method for fabricating shadow trench insulation structure
US6005279A (en) * 1997-12-18 1999-12-21 Advanced Micro Devices, Inc. Trench edge spacer formation
US5882983A (en) * 1997-12-19 1999-03-16 Advanced Micro Devices, Inc. Trench isolation structure partially bound between a pair of low K dielectric structures
US6228741B1 (en) 1998-01-13 2001-05-08 Texas Instruments Incorporated Method for trench isolation of semiconductor devices
US6054343A (en) * 1998-01-26 2000-04-25 Texas Instruments Incorporated Nitride trench fill process for increasing shallow trench isolation (STI) robustness
US5950090A (en) * 1998-11-16 1999-09-07 United Microelectronics Corp. Method for fabricating a metal-oxide semiconductor transistor

Also Published As

Publication number Publication date
CN1384976A (zh) 2002-12-11
KR20010100005A (ko) 2001-11-09
CN1199256C (zh) 2005-04-27
EP1145304B1 (de) 2011-03-16
KR100728398B1 (ko) 2007-06-13
KR100707535B1 (ko) 2007-04-12
JP2003513469A (ja) 2003-04-08
WO2001033626A1 (en) 2001-05-10
US6251747B1 (en) 2001-06-26
EP1145304A1 (de) 2001-10-17
KR20010093238A (ko) 2001-10-27

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