DE60043636D1 - Hochfrequenzvorrichtung - Google Patents
HochfrequenzvorrichtungInfo
- Publication number
- DE60043636D1 DE60043636D1 DE60043636T DE60043636T DE60043636D1 DE 60043636 D1 DE60043636 D1 DE 60043636D1 DE 60043636 T DE60043636 T DE 60043636T DE 60043636 T DE60043636 T DE 60043636T DE 60043636 D1 DE60043636 D1 DE 60043636D1
- Authority
- DE
- Germany
- Prior art keywords
- frequency device
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
- H01P3/088—Stacked transmission lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26369799A JP3500335B2 (ja) | 1999-09-17 | 1999-09-17 | 高周波回路装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60043636D1 true DE60043636D1 (de) | 2010-02-25 |
Family
ID=17393089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60043636T Expired - Lifetime DE60043636D1 (de) | 1999-09-17 | 2000-09-15 | Hochfrequenzvorrichtung |
Country Status (4)
Country | Link |
---|---|
US (1) | US6621162B1 (de) |
EP (1) | EP1085594B1 (de) |
JP (1) | JP3500335B2 (de) |
DE (1) | DE60043636D1 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2669223B2 (ja) * | 1991-10-14 | 1997-10-27 | 三菱電機株式会社 | ランデブードッキング用光学センサー装置 |
JP2003110049A (ja) | 2001-09-28 | 2003-04-11 | Fujitsu Ten Ltd | 高周波icパッケージ、高周波icパッケージを使用する高周波ユニット及び、その製造方法 |
JP4388284B2 (ja) * | 2003-01-31 | 2009-12-24 | アイ電子株式会社 | 高周波回路用パッケージ及びその実装構造 |
US6917265B2 (en) * | 2003-05-22 | 2005-07-12 | Synergy Microwave Corporation | Microwave frequency surface mount components and methods of forming same |
JP2005026263A (ja) * | 2003-06-30 | 2005-01-27 | Nec Compound Semiconductor Devices Ltd | 混成集積回路 |
US7948069B2 (en) * | 2004-01-28 | 2011-05-24 | International Rectifier Corporation | Surface mountable hermetically sealed package |
JP4664670B2 (ja) * | 2004-12-24 | 2011-04-06 | 株式会社東芝 | 半導体装置 |
JP4690938B2 (ja) * | 2006-05-16 | 2011-06-01 | 株式会社東芝 | 高周波素子モジュール |
WO2008108350A1 (ja) * | 2007-03-08 | 2008-09-12 | Nec Corporation | 容量素子、プリント配線基板、半導体パッケージ及び半導体回路 |
JP5477157B2 (ja) * | 2010-05-17 | 2014-04-23 | 富士電機株式会社 | 半導体装置 |
JP5827476B2 (ja) * | 2011-03-08 | 2015-12-02 | 株式会社東芝 | 半導体モジュール及びその製造方法 |
JP5851439B2 (ja) * | 2013-03-07 | 2016-02-03 | 株式会社東芝 | 高周波半導体用パッケージ |
JP2016096300A (ja) * | 2014-11-17 | 2016-05-26 | 三菱電機株式会社 | プリント回路板 |
JP6373779B2 (ja) * | 2015-03-12 | 2018-08-15 | 株式会社東芝 | 高周波半導体装置 |
US9960127B2 (en) * | 2016-05-18 | 2018-05-01 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
US10134658B2 (en) | 2016-08-10 | 2018-11-20 | Macom Technology Solutions Holdings, Inc. | High power transistors |
JP6440917B1 (ja) * | 2018-04-12 | 2018-12-19 | 三菱電機株式会社 | 半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61239649A (ja) * | 1985-04-13 | 1986-10-24 | Fujitsu Ltd | 高速集積回路パツケ−ジ |
US4873566A (en) * | 1985-10-28 | 1989-10-10 | American Telephone And Telegraph Company | Multilayer ceramic laser package |
US5136271A (en) | 1989-01-09 | 1992-08-04 | Mitsubishi Denki Kabushiki Kaisha | Microwave integrated circuit mountings |
JP3267409B2 (ja) * | 1992-11-24 | 2002-03-18 | 株式会社日立製作所 | 半導体集積回路装置 |
US5307240A (en) * | 1992-12-02 | 1994-04-26 | Intel Corporation | Chiplid, multichip semiconductor package design concept |
JPH07321140A (ja) * | 1994-05-19 | 1995-12-08 | Toshiba Corp | 半導体装置 |
US5766975A (en) | 1995-01-09 | 1998-06-16 | Integrated Device Technology, Inc. | Packaged integrated circuit having thermal enhancement and reduced footprint size |
US5796165A (en) | 1996-03-19 | 1998-08-18 | Matsushita Electronics Corporation | High-frequency integrated circuit device having a multilayer structure |
JP2950290B2 (ja) | 1997-06-27 | 1999-09-20 | 日本電気株式会社 | 高周波集積回路装置およびその製造方法 |
JP3859340B2 (ja) * | 1998-01-06 | 2006-12-20 | 三菱電機株式会社 | 半導体装置 |
JPH11238846A (ja) * | 1998-02-20 | 1999-08-31 | Rohm Co Ltd | 半導体装置 |
US5973928A (en) * | 1998-08-18 | 1999-10-26 | International Business Machines Corporation | Multi-layer ceramic substrate decoupling |
-
1999
- 1999-09-17 JP JP26369799A patent/JP3500335B2/ja not_active Expired - Fee Related
-
2000
- 2000-09-15 US US09/662,869 patent/US6621162B1/en not_active Expired - Lifetime
- 2000-09-15 DE DE60043636T patent/DE60043636D1/de not_active Expired - Lifetime
- 2000-09-15 EP EP00119475A patent/EP1085594B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1085594A2 (de) | 2001-03-21 |
EP1085594B1 (de) | 2010-01-06 |
US6621162B1 (en) | 2003-09-16 |
JP2001085569A (ja) | 2001-03-30 |
JP3500335B2 (ja) | 2004-02-23 |
EP1085594A3 (de) | 2003-01-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |