DE60005873D1 - Addierschaltung mit Addier-End-Signal - Google Patents

Addierschaltung mit Addier-End-Signal

Info

Publication number
DE60005873D1
DE60005873D1 DE60005873T DE60005873T DE60005873D1 DE 60005873 D1 DE60005873 D1 DE 60005873D1 DE 60005873 T DE60005873 T DE 60005873T DE 60005873 T DE60005873 T DE 60005873T DE 60005873 D1 DE60005873 D1 DE 60005873D1
Authority
DE
Germany
Prior art keywords
end signal
addition circuit
add end
add
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60005873T
Other languages
English (en)
Other versions
DE60005873T2 (de
Inventor
Koichi Kuroiwa
Shoji Taniguchi
Masami Kanasugi
Mahiro Hikita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60005873D1 publication Critical patent/DE60005873D1/de
Publication of DE60005873T2 publication Critical patent/DE60005873T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE2000605873 1999-03-17 2000-03-06 Addierschaltung mit Addier-End-Signal Expired - Lifetime DE60005873T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP07262999A JP3487783B2 (ja) 1999-03-17 1999-03-17 加算回路、それを利用した積分回路、及びそれを利用した同期確立回路
JP7262999 1999-03-17

Publications (2)

Publication Number Publication Date
DE60005873D1 true DE60005873D1 (de) 2003-11-20
DE60005873T2 DE60005873T2 (de) 2004-05-19

Family

ID=13494880

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2000605873 Expired - Lifetime DE60005873T2 (de) 1999-03-17 2000-03-06 Addierschaltung mit Addier-End-Signal

Country Status (5)

Country Link
US (1) US6647405B1 (de)
EP (1) EP1037139B1 (de)
JP (1) JP3487783B2 (de)
KR (1) KR100615008B1 (de)
DE (1) DE60005873T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001086032A (ja) * 1999-09-10 2001-03-30 Pioneer Electronic Corp 通信装置及び通信方法
JP5958138B2 (ja) * 2012-07-19 2016-07-27 セイコーエプソン株式会社 非同期全加算回路、非同期相関演算回路、演算装置及び相関演算装置
US9262123B2 (en) * 2013-07-31 2016-02-16 Arm Limited Data processing apparatus and method for performing a narrowing-and-rounding arithmetic operation

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL98963C (de) * 1957-01-16
US3138703A (en) * 1959-12-29 1964-06-23 Ibm Full adder
US3932734A (en) * 1974-03-08 1976-01-13 Hawker Siddeley Dynamics Limited Binary parallel adder employing high speed gating circuitry
US3970833A (en) * 1975-06-18 1976-07-20 The United States Of America As Represented By The Secretary Of The Navy High-speed adder
US4052604A (en) * 1976-01-19 1977-10-04 Hewlett-Packard Company Binary adder
JPS6055438A (ja) * 1983-09-05 1985-03-30 Matsushita Electric Ind Co Ltd ２入力加算器
JPS60134932A (ja) * 1983-12-24 1985-07-18 Toshiba Corp プリチヤ−ジ型の桁上げ連鎖加算回路
US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers
JPS6382515A (ja) * 1986-09-27 1988-04-13 Toshiba Corp 加算器
EP0571693B1 (de) * 1992-05-27 1996-04-10 STMicroelectronics S.r.l. Schnelle Addierkette
US5337269A (en) * 1993-03-05 1994-08-09 Cyrix Corporation Carry skip adder with independent carry-in and carry skip paths
JPH09167081A (ja) 1995-12-15 1997-06-24 Toshiba Corp 加算回路
JPH09261121A (ja) * 1996-03-22 1997-10-03 Kazuo Tsubouchi 符号分割多重通信装置
US6031887A (en) * 1997-07-30 2000-02-29 Lucent Technolgies Inc. High-speed binary synchronous counter

Also Published As

Publication number Publication date
DE60005873T2 (de) 2004-05-19
JP2000267838A (ja) 2000-09-29
JP3487783B2 (ja) 2004-01-19
KR100615008B1 (ko) 2006-08-25
EP1037139A1 (de) 2000-09-20
KR20010006813A (ko) 2001-01-26
US6647405B1 (en) 2003-11-11
EP1037139B1 (de) 2003-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE