DE60028099D1 - Verbesserte Treiberschaltung - Google Patents

Verbesserte Treiberschaltung

Info

Publication number
DE60028099D1
DE60028099D1 DE60028099T DE60028099T DE60028099D1 DE 60028099 D1 DE60028099 D1 DE 60028099D1 DE 60028099 T DE60028099 T DE 60028099T DE 60028099 T DE60028099 T DE 60028099T DE 60028099 D1 DE60028099 D1 DE 60028099D1
Authority
DE
Germany
Prior art keywords
driver circuit
improved driver
improved
circuit
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60028099T
Other languages
English (en)
Other versions
DE60028099T2 (de
Inventor
David R Hanson
Gerhard Mueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60028099D1 publication Critical patent/DE60028099D1/de
Publication of DE60028099T2 publication Critical patent/DE60028099T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE60028099T 1999-01-05 2000-01-05 Verbesserte Treiberschaltung Expired - Fee Related DE60028099T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/225,664 US6127878A (en) 1999-01-05 1999-01-05 Driver circuit with negative lower power rail
US225664 1999-01-05

Publications (2)

Publication Number Publication Date
DE60028099D1 true DE60028099D1 (de) 2006-06-29
DE60028099T2 DE60028099T2 (de) 2006-12-07

Family

ID=22845745

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60028099T Expired - Fee Related DE60028099T2 (de) 1999-01-05 2000-01-05 Verbesserte Treiberschaltung

Country Status (6)

Country Link
US (1) US6127878A (de)
EP (1) EP1018745B1 (de)
JP (1) JP2000235793A (de)
KR (1) KR20000071229A (de)
CN (1) CN1259742A (de)
DE (1) DE60028099T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388475B1 (en) * 1999-12-29 2002-05-14 Intle Corporation Voltage tolerant high drive pull-up driver for an I/O buffer
US7142446B2 (en) * 2004-07-29 2006-11-28 Micron Technology, Inc. Apparatus and method to reduce undesirable effects caused by a fault in a memory device
US7430148B2 (en) * 2005-11-17 2008-09-30 Altera Corporation Volatile memory elements with boosted output voltages for programmable logic device integrated circuits
KR101151102B1 (ko) * 2010-10-26 2012-06-01 에스케이하이닉스 주식회사 데이터 출력 드라이버 및 이를 구비한 집적 회로
US10057090B2 (en) * 2016-09-26 2018-08-21 Qualcomm Incorporated Apparatus and method for transmitting data signal based on various transmission modes
US10755759B2 (en) * 2018-06-28 2020-08-25 International Business Machines Corporation Symmetrically programmable resistive synapse for RPU using current-programmed single domain wall ferroelectric
CN114255802B (zh) 2020-09-22 2023-09-15 长鑫存储技术有限公司 集成电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959561A (en) * 1989-01-04 1990-09-25 Motorola, Inc. MOS output buffer with reduced supply line disturbance
JPH02246516A (ja) * 1989-03-20 1990-10-02 Hitachi Ltd 半導体装置
US5258662A (en) * 1992-04-06 1993-11-02 Linear Technology Corp. Micropower gate charge pump for power MOSFETS
US5808956A (en) * 1995-12-20 1998-09-15 Seiko Epson Corporation Bus-line drive circuit and semiconductor storage device comprising the same
TW333698B (en) * 1996-01-30 1998-06-11 Hitachi Ltd The method for output circuit to select switch transistor & semiconductor memory
EP0821362B1 (de) * 1996-07-24 2004-05-26 STMicroelectronics S.r.l. Ausgabestufe für Speicheranlage und für Niederspannungsanwendungen

Also Published As

Publication number Publication date
EP1018745A1 (de) 2000-07-12
EP1018745B1 (de) 2006-05-24
DE60028099T2 (de) 2006-12-07
CN1259742A (zh) 2000-07-12
US6127878A (en) 2000-10-03
JP2000235793A (ja) 2000-08-29
KR20000071229A (ko) 2000-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8339 Ceased/non-payment of the annual fee