DE3927192C2 - - Google Patents

Info

Publication number
DE3927192C2
DE3927192C2 DE19893927192 DE3927192A DE3927192C2 DE 3927192 C2 DE3927192 C2 DE 3927192C2 DE 19893927192 DE19893927192 DE 19893927192 DE 3927192 A DE3927192 A DE 3927192A DE 3927192 C2 DE3927192 C2 DE 3927192C2
Authority
DE
Germany
Prior art keywords
level
transistor
mos transistor
circuit arrangement
range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19893927192
Other languages
German (de)
English (en)
Other versions
DE3927192A1 (de
Inventor
Josef 7101 Untergruppenbach De Feldmeier
Peter Dr. 7100 Heilbronn De Tomaszewski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Munich GmbH
Original Assignee
Telefunken Electronic GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Electronic GmbH filed Critical Telefunken Electronic GmbH
Priority to DE19893927192 priority Critical patent/DE3927192A1/de
Publication of DE3927192A1 publication Critical patent/DE3927192A1/de
Application granted granted Critical
Publication of DE3927192C2 publication Critical patent/DE3927192C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE19893927192 1989-08-17 1989-08-17 Pegelumsetzer Granted DE3927192A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19893927192 DE3927192A1 (de) 1989-08-17 1989-08-17 Pegelumsetzer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19893927192 DE3927192A1 (de) 1989-08-17 1989-08-17 Pegelumsetzer

Publications (2)

Publication Number Publication Date
DE3927192A1 DE3927192A1 (de) 1991-02-21
DE3927192C2 true DE3927192C2 (fr) 1992-01-09

Family

ID=6387304

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19893927192 Granted DE3927192A1 (de) 1989-08-17 1989-08-17 Pegelumsetzer

Country Status (1)

Country Link
DE (1) DE3927192A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2691307A1 (fr) * 1992-05-18 1993-11-19 Lausanne Ecole Polytechnique F Circuit intermédiaire entre un circuit logique à basse tension et un étage de sortie à haute tension réalisés dans une technologie CMOS standard.

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
DE3323446A1 (de) * 1983-06-29 1985-01-10 Siemens AG, 1000 Berlin und 8000 München Eingangssignalpegelwandler fuer eine mos-digitalschaltung
DE3324030A1 (de) * 1983-07-04 1985-01-17 Siemens AG, 1000 Berlin und 8000 München Eingangssignalpegelwandler fuer eine integrierte cmos-digitalschaltung
JPH07107973B2 (ja) * 1984-03-26 1995-11-15 株式会社日立製作所 スイツチング回路
DE3424274A1 (de) * 1984-07-02 1986-01-09 Siemens AG, 1000 Berlin und 8000 München Integrierte schaltung zur abgabe einer zwischen einem positiven und einem negativen spannungspegel alternierenden taktspannung

Also Published As

Publication number Publication date
DE3927192A1 (de) 1991-02-21

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Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: TEMIC TELEFUNKEN MICROELECTRONIC GMBH, 7100 HEILBR

8320 Willingness to grant licenses declared (paragraph 23)
8327 Change in the person/name/address of the patent owner

Owner name: TEMIC SEMICONDUCTOR GMBH, 74072 HEILBRONN, DE

8327 Change in the person/name/address of the patent owner

Owner name: ATMEL GERMANY GMBH, 74072 HEILBRONN, DE

8327 Change in the person/name/address of the patent owner

Owner name: ATMEL AUTOMOTIVE GMBH, 74072 HEILBRONN, DE