DE3889634D1 - Synchronisierer mit endlicher metastabiler Dauer. - Google Patents

Synchronisierer mit endlicher metastabiler Dauer.

Info

Publication number
DE3889634D1
DE3889634D1 DE3889634T DE3889634T DE3889634D1 DE 3889634 D1 DE3889634 D1 DE 3889634D1 DE 3889634 T DE3889634 T DE 3889634T DE 3889634 T DE3889634 T DE 3889634T DE 3889634 D1 DE3889634 D1 DE 3889634D1
Authority
DE
Germany
Prior art keywords
synchronizer
finite
metastable
duration
metastable duration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889634T
Other languages
English (en)
Other versions
DE3889634T2 (de
Inventor
Richard Sowell
Robert Pieters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE3889634D1 publication Critical patent/DE3889634D1/de
Publication of DE3889634T2 publication Critical patent/DE3889634T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
DE3889634T 1987-11-24 1988-11-18 Synchronisierer mit endlicher metastabiler Dauer. Expired - Fee Related DE3889634T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/124,875 US4820939A (en) 1987-11-24 1987-11-24 Finite metastable time synchronizer

Publications (2)

Publication Number Publication Date
DE3889634D1 true DE3889634D1 (de) 1994-06-23
DE3889634T2 DE3889634T2 (de) 1994-12-08

Family

ID=22417223

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889634T Expired - Fee Related DE3889634T2 (de) 1987-11-24 1988-11-18 Synchronisierer mit endlicher metastabiler Dauer.

Country Status (6)

Country Link
US (1) US4820939A (de)
EP (1) EP0317901B1 (de)
JP (1) JPH02111116A (de)
KR (1) KR0131878B1 (de)
CA (1) CA1290406C (de)
DE (1) DE3889634T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3627964C2 (de) * 1985-08-26 2000-11-02 Samsung Electronic Devices Ferroelektrische kristallin-flüssige Derivate verzweigter acyclischer chiraler alpha-Chlorcarbonsäuren, Verfahren zu ihrer Herstellung und ihre Verwendung in Gemischen für schnell schaltende Displays in der Optoelektronik
US4985643A (en) * 1988-06-24 1991-01-15 National Semiconductor Corporation Speed enhancement technique for CMOS circuits
EP0375247B1 (de) * 1988-12-21 1996-02-28 Texas Instruments Incorporated Einen metastabilen Zustand zulassende Kippschaltung
JP2621993B2 (ja) * 1989-09-05 1997-06-18 株式会社東芝 フリップフロップ回路
US4999528A (en) * 1989-11-14 1991-03-12 Keech Eugene E Metastable-proof flip-flop
US5023486A (en) * 1990-03-30 1991-06-11 Atmel Corporation Logic output control circuit for a latch
US5047658A (en) * 1990-06-01 1991-09-10 Ncr Corporation High frequency asynchronous data synchronizer
JPH0661805A (ja) * 1992-08-06 1994-03-04 Nec Ic Microcomput Syst Ltd 同期化回路
US6590423B1 (en) * 1994-10-11 2003-07-08 Derek Wong Digital circuits exhibiting reduced power consumption
JPH08147143A (ja) * 1994-11-21 1996-06-07 Mitsubishi Electric Corp 半導体集積回路
US5638018A (en) * 1995-06-02 1997-06-10 Advanced Micro Devices, Inc. P-type flip-flop
US5654660A (en) * 1995-09-27 1997-08-05 Hewlett-Packard Company Level shifted high impedance input multiplexor
US5721886A (en) * 1995-11-30 1998-02-24 Ncr Corporation Synchronizer circuit which controls switching of clocks based upon synchronicity, asynchronicity, or change in frequency
US5719516A (en) * 1995-12-20 1998-02-17 Advanced Micro Devices, Inc. Lock generator circuit for use with a dual edge register that provides a separate enable for each use of an input clock signal
JP3797778B2 (ja) * 1998-01-19 2006-07-19 東芝マイクロエレクトロニクス株式会社 データ伝送回路
JP4397066B2 (ja) * 1999-03-24 2010-01-13 日本テキサス・インスツルメンツ株式会社 ラッチ回路
US6410966B2 (en) 2000-03-22 2002-06-25 Texas Instruments Incorporated Ratio circuit
FR2884988A1 (fr) * 2005-04-22 2006-10-27 St Microelectronics Sa Bascule protegee contre les pics de courant ou de tension
US7965119B2 (en) * 2006-06-20 2011-06-21 Freescale Semiconductor, Inc. Device and method for handling metastable signals
US8115531B1 (en) * 2008-03-31 2012-02-14 Lsi Corporation D flip-flop having enhanced immunity to single-event upsets and method of operation thereof
US7977983B1 (en) 2008-05-01 2011-07-12 Freescale Semiconductor, Inc. Device having synchronizing capabilities
US8904336B1 (en) * 2013-06-29 2014-12-02 Synopsys, Inc. Determination of meta-stable latch bias voltages
US9384812B2 (en) * 2014-01-28 2016-07-05 Qualcomm Incorporated Three-phase GSHE-MTJ non-volatile flip-flop
CN108958022B (zh) * 2018-07-09 2020-05-12 燕山大学 非线性主-从时延系统的时滞相关有限时间同步控制方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4093878A (en) * 1976-11-29 1978-06-06 Ncr Corporation De-glitchablenon-metastable flip-flop circuit
US4398105A (en) * 1981-01-22 1983-08-09 Signetics Corporation Arbiter circuit
DE3106183A1 (de) * 1981-02-19 1982-09-02 Siemens AG, 1000 Berlin und 8000 München Verfahren und anordnung zur fehlerfreien synchronisation asynchroner impulse
US4544851A (en) * 1981-08-31 1985-10-01 Texas Instruments Incorporated Synchronizer circuit with dual input
US4529892A (en) * 1982-11-23 1985-07-16 Rca Corporation Detection circuitry with multiple overlapping thresholds
US4591737A (en) * 1982-12-13 1986-05-27 Advanced Micro Devices, Inc. Master-slave multivibrator with improved metastable response characteristic
US4495629A (en) * 1983-01-25 1985-01-22 Storage Technology Partners CMOS scannable latch
US4667339A (en) * 1983-12-05 1987-05-19 Texas Instruments Incorporated Level sensitive latch stage
FR2578125B1 (fr) * 1985-02-28 1987-04-10 Efcis Bascule bistable statique en technologie cmos
GB2174856A (en) * 1985-05-08 1986-11-12 Racal Microelect System Hysteresis latch arrangement
JPS6295016A (ja) * 1985-10-21 1987-05-01 Mitsubishi Electric Corp ラツチ回路

Also Published As

Publication number Publication date
KR0131878B1 (ko) 1998-10-01
JPH02111116A (ja) 1990-04-24
EP0317901B1 (de) 1994-05-18
CA1290406C (en) 1991-10-08
EP0317901A3 (en) 1990-07-11
EP0317901A2 (de) 1989-05-31
DE3889634T2 (de) 1994-12-08
US4820939A (en) 1989-04-11
KR890009117A (ko) 1989-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee