DE3889210D1 - Integrierte logische Schaltung mit Reduzierung der Effekte hochenergetischer Ladungsträger und Instabilitätsdämpfung. - Google Patents

Integrierte logische Schaltung mit Reduzierung der Effekte hochenergetischer Ladungsträger und Instabilitätsdämpfung.

Info

Publication number
DE3889210D1
DE3889210D1 DE3889210T DE3889210T DE3889210D1 DE 3889210 D1 DE3889210 D1 DE 3889210D1 DE 3889210 T DE3889210 T DE 3889210T DE 3889210 T DE3889210 T DE 3889210T DE 3889210 D1 DE3889210 D1 DE 3889210D1
Authority
DE
Germany
Prior art keywords
instability
damping
reduction
effects
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889210T
Other languages
English (en)
Other versions
DE3889210T2 (de
Inventor
Jan Dikken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE3889210D1 publication Critical patent/DE3889210D1/de
Application granted granted Critical
Publication of DE3889210T2 publication Critical patent/DE3889210T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE3889210T 1987-11-20 1988-11-15 Integrierte logische Schaltung mit Reduzierung der Effekte hochenergetischer Ladungsträger und Instabilitätsdämpfung. Expired - Fee Related DE3889210T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8702781A NL8702781A (nl) 1987-11-20 1987-11-20 Geintegreerde logische schakeling met "hot-carrier-stress"-reduktie en instabiliteiten-demping.

Publications (2)

Publication Number Publication Date
DE3889210D1 true DE3889210D1 (de) 1994-05-26
DE3889210T2 DE3889210T2 (de) 1994-10-20

Family

ID=19850947

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889210T Expired - Fee Related DE3889210T2 (de) 1987-11-20 1988-11-15 Integrierte logische Schaltung mit Reduzierung der Effekte hochenergetischer Ladungsträger und Instabilitätsdämpfung.

Country Status (6)

Country Link
US (1) US4952822A (de)
EP (1) EP0322000B1 (de)
JP (1) JP2685251B2 (de)
KR (1) KR960009401B1 (de)
DE (1) DE3889210T2 (de)
NL (1) NL8702781A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3813802A1 (de) * 1988-04-23 1989-11-09 Glyco Metall Werke Schichtwerkstoff oder schichtwerkstueck mit einer auf einer traegerschicht angebrachten funktionsschicht, insbesondere gleitschicht mit der struktur einer festen, aber schmelzbaren dispersion
US5049764A (en) * 1990-01-25 1991-09-17 North American Philips Corporation, Signetics Div. Active bypass for inhibiting high-frequency supply voltage variations in integrated circuits
US5428837A (en) * 1993-01-13 1995-06-27 Anadigics, Inc. Method and apparatus for reducing local oscillator leakage in integrated circuit receivers

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160440A (en) * 1974-11-22 1976-05-26 Hitachi Ltd Kotaiatsuyo mis fet suitsuchingukairo
US4209713A (en) * 1975-07-18 1980-06-24 Tokyo Shibaura Electric Co., Ltd. Semiconductor integrated circuit device in which difficulties caused by parasitic transistors are eliminated
DE3138558A1 (de) * 1981-09-28 1983-04-07 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur erzeugung eines von schwankungen einer versorgungsgleichspannung freien gleichspannungspegels
JPS62501043A (ja) * 1984-12-10 1987-04-23 アメリカン テレフオン アンド テレグラフ カムパニ− 高信頼度相補論理回路
US4704547A (en) * 1984-12-10 1987-11-03 American Telephone And Telegraph Company, At&T Bell Laboratories IGFET gating circuit having reduced electric field degradation
US4710726A (en) * 1986-02-27 1987-12-01 Columbia University In The City Of New York Semiconductive MOS resistance network
JPS62230220A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 相補性絶縁ゲ−ト型論理回路
US4677312A (en) * 1986-04-25 1987-06-30 International Business Machines Corporation High voltage swing open collector driver
US4771189A (en) * 1986-05-02 1988-09-13 Ford Microelectronics, Inc. FET gate current limiter circuit
US4791323A (en) * 1986-10-23 1988-12-13 Silicon Systems, Inc. Level translation circuit

Also Published As

Publication number Publication date
KR960009401B1 (ko) 1996-07-18
JP2685251B2 (ja) 1997-12-03
EP0322000B1 (de) 1994-04-20
US4952822A (en) 1990-08-28
EP0322000A1 (de) 1989-06-28
KR890009093A (ko) 1989-07-15
NL8702781A (nl) 1989-06-16
JPH01162013A (ja) 1989-06-26
DE3889210T2 (de) 1994-10-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee