DE3886115D1 - Verfahren zum Anbringen dünner Schichten aus oxidischem supraleitendem Material. - Google Patents

Verfahren zum Anbringen dünner Schichten aus oxidischem supraleitendem Material.

Info

Publication number
DE3886115D1
DE3886115D1 DE88201513T DE3886115T DE3886115D1 DE 3886115 D1 DE3886115 D1 DE 3886115D1 DE 88201513 T DE88201513 T DE 88201513T DE 3886115 T DE3886115 T DE 3886115T DE 3886115 D1 DE3886115 D1 DE 3886115D1
Authority
DE
Germany
Prior art keywords
thin layers
superconductive
oxide superconducting
superconducting material
applying thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88201513T
Other languages
English (en)
Other versions
DE3886115T2 (de
Inventor
Maritza Gerarda Joseph Heijman
Peter Cornelis Zalm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3886115D1 publication Critical patent/DE3886115D1/de
Publication of DE3886115T2 publication Critical patent/DE3886115T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/73—Vacuum treating or coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/742—Annealing

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Oxygen, Ozone, And Oxides In General (AREA)
DE3886115T 1987-07-21 1988-07-14 Verfahren zum Anbringen dünner Schichten aus oxidischem supraleitendem Material. Expired - Fee Related DE3886115T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8701718A NL8701718A (nl) 1987-07-21 1987-07-21 Werkwijze voor het aanbrengen van dunne lagen van oxidisch supergeleidend materiaal.

Publications (2)

Publication Number Publication Date
DE3886115D1 true DE3886115D1 (de) 1994-01-20
DE3886115T2 DE3886115T2 (de) 1994-06-09

Family

ID=19850351

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3886115T Expired - Fee Related DE3886115T2 (de) 1987-07-21 1988-07-14 Verfahren zum Anbringen dünner Schichten aus oxidischem supraleitendem Material.

Country Status (8)

Country Link
US (2) US4900709A (de)
EP (1) EP0300567B1 (de)
JP (1) JPS6441282A (de)
KR (1) KR970005156B1 (de)
AT (1) ATE98401T1 (de)
DE (1) DE3886115T2 (de)
NL (1) NL8701718A (de)
SU (1) SU1738104A3 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3884511T2 (de) * 1987-07-27 1994-02-03 Ovonic Synthetic Materials Verfahren zum Stabilisieren eines hoch-Tc-supraleitenden Materials und so stabilisiertes Material.
JPS6457438A (en) * 1987-08-28 1989-03-03 Mitsubishi Electric Corp Recording medium
JPH01171247A (ja) * 1987-12-25 1989-07-06 Mitsubishi Metal Corp 超伝導体配線の構造
GB2215548B (en) * 1988-02-26 1991-10-23 Gen Electric Co Plc A method of fabricating superconducting electronic devices
JPH0244784A (ja) * 1988-08-05 1990-02-14 Canon Inc 超伝導パターンの形成方法
US5246916A (en) * 1989-03-22 1993-09-21 Sri International Method of forming shaped superconductor materials by electrophoretic deposition of superconductor particulate coated with fusible binder
US5229360A (en) * 1989-07-24 1993-07-20 The Furukawa Electric Co., Ltd. Method for forming a multilayer superconducting circuit
US5135908A (en) * 1989-08-07 1992-08-04 The Trustees Of Columbia University In The City Of New York Method of patterning superconducting films
EP0450394A3 (de) * 1990-03-20 1991-10-23 Fujitsu Limited Verfahren und Vorrichtung zur Herstellung von supraleitenden Schichten
US5856275A (en) * 1990-11-01 1999-01-05 Sumitomo Electric Industries, Ltd. Superconducting wiring lines and process for fabricating the same
JPH0697522A (ja) * 1990-11-30 1994-04-08 Internatl Business Mach Corp <Ibm> 超伝導材料の薄膜の製造方法
US5252551A (en) * 1991-12-27 1993-10-12 The United States Of America As Represented By The Department Of Energy Superconducting composite with multilayer patterns and multiple buffer layers
US5593918A (en) * 1994-04-22 1997-01-14 Lsi Logic Corporation Techniques for forming superconductive lines
JP3076503B2 (ja) * 1994-12-08 2000-08-14 株式会社日立製作所 超電導素子およびその製造方法
DE102006030787B4 (de) * 2006-06-30 2008-11-27 Zenergy Power Gmbh Negativstrukturierung von Dünnschicht Hochtemperatur-Supraleitern

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4316785A (en) * 1979-11-05 1982-02-23 Nippon Telegraph & Telephone Public Corporation Oxide superconductor Josephson junction and fabrication method therefor
US4255474A (en) * 1980-01-04 1981-03-10 Rockwell International Corporation Composite having transparent conductor pattern
US4290843A (en) * 1980-02-19 1981-09-22 Texas Instruments Incorporated Epitaxial growth of magnetic memory film on implanted substrate
KR950010206B1 (ko) * 1987-03-09 1995-09-11 가부시끼가이샤 한도다이 에네르기 겐꾸쇼 전자 장치 및 그 제조 방법
US4960751A (en) * 1987-04-01 1990-10-02 Semiconductor Energy Laboratory Co., Ltd. Electric circuit having superconducting multilayered structure and manufacturing method for same
JPS63291485A (ja) * 1987-05-25 1988-11-29 Fujikura Ltd 酸化物超電導回路の製造方法
CN1017110B (zh) * 1987-08-13 1992-06-17 株式会社半导体能源研究所 一种超导器件

Also Published As

Publication number Publication date
KR970005156B1 (ko) 1997-04-12
KR890003053A (ko) 1989-04-12
ATE98401T1 (de) 1993-12-15
EP0300567A2 (de) 1989-01-25
US4900709A (en) 1990-02-13
EP0300567A3 (en) 1989-05-10
US4957899A (en) 1990-09-18
DE3886115T2 (de) 1994-06-09
SU1738104A3 (ru) 1992-05-30
NL8701718A (nl) 1989-02-16
EP0300567B1 (de) 1993-12-08
JPS6441282A (en) 1989-02-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee