DE3885436D1 - Halbleiterkristallstruktur und deren Herstellungsverfahren. - Google Patents

Halbleiterkristallstruktur und deren Herstellungsverfahren.

Info

Publication number
DE3885436D1
DE3885436D1 DE88312391T DE3885436T DE3885436D1 DE 3885436 D1 DE3885436 D1 DE 3885436D1 DE 88312391 T DE88312391 T DE 88312391T DE 3885436 T DE3885436 T DE 3885436T DE 3885436 D1 DE3885436 D1 DE 3885436D1
Authority
DE
Germany
Prior art keywords
layer
semiconductor crystal
semiconductor
atom mono
stratified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88312391T
Other languages
English (en)
Other versions
DE3885436T2 (de
Inventor
Kazuyoshi Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP33603687A external-priority patent/JPH0748474B2/ja
Priority claimed from JP33603987A external-priority patent/JPH0748475B2/ja
Priority claimed from JP33604087A external-priority patent/JPH0748476B2/ja
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3885436D1 publication Critical patent/DE3885436D1/de
Publication of DE3885436T2 publication Critical patent/DE3885436T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE3885436T 1987-12-29 1988-12-29 Halbleiterkristallstruktur und deren Herstellungsverfahren. Expired - Fee Related DE3885436T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP33603687A JPH0748474B2 (ja) 1987-12-29 1987-12-29 半導体結晶の構造
JP33603987A JPH0748475B2 (ja) 1987-12-29 1987-12-29 半導体結晶の構造
JP33604087A JPH0748476B2 (ja) 1987-12-29 1987-12-29 半導体結晶の構造

Publications (2)

Publication Number Publication Date
DE3885436D1 true DE3885436D1 (de) 1993-12-09
DE3885436T2 DE3885436T2 (de) 1994-05-19

Family

ID=27340760

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3885436T Expired - Fee Related DE3885436T2 (de) 1987-12-29 1988-12-29 Halbleiterkristallstruktur und deren Herstellungsverfahren.

Country Status (3)

Country Link
US (1) US4980750A (de)
EP (1) EP0323249B1 (de)
DE (1) DE3885436T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448084A (en) * 1991-05-24 1995-09-05 Raytheon Company Field effect transistors on spinel substrates
JP2776716B2 (ja) * 1993-01-14 1998-07-16 日本電気株式会社 電界効果型トランジスタ
US6833294B1 (en) * 2003-06-26 2004-12-21 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE634299A (de) * 1962-06-29 1900-01-01
NL295293A (de) * 1962-07-13
US3764424A (en) * 1971-05-03 1973-10-09 Bell Telephone Labor Inc Fabrication of gallium arsenide devices
US4205329A (en) * 1976-03-29 1980-05-27 Bell Telephone Laboratories, Incorporated Periodic monolayer semiconductor structures grown by molecular beam epitaxy
US4261771A (en) * 1979-10-31 1981-04-14 Bell Telephone Laboratories, Incorporated Method of fabricating periodic monolayer semiconductor structures by molecular beam epitaxy
JPS59207667A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd 半導体装置
NL8301745A (nl) * 1983-05-17 1984-12-17 Philips Nv Halfgeleiderinrichting.
JPS60176276A (ja) * 1984-02-22 1985-09-10 Nec Corp ガリウム砒素集積回路
JPH0728080B2 (ja) * 1984-09-25 1995-03-29 日本電気株式会社 半導体超格子構造体
US4835583A (en) * 1985-08-30 1989-05-30 Hitachi, Ltd. Semiconductor device having strained superlattice buffer layers with In-doped GaAs substrate
JPH0815212B2 (ja) * 1985-08-30 1996-02-14 ソニー株式会社 半導体装置
JPH084138B2 (ja) * 1986-05-23 1996-01-17 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
US4980750A (en) 1990-12-25
DE3885436T2 (de) 1994-05-19
EP0323249A2 (de) 1989-07-05
EP0323249B1 (de) 1993-11-03
EP0323249A3 (en) 1989-10-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee