DE3885121D1 - Herstellung von Widerständen aus polykristallinem Silizium. - Google Patents

Herstellung von Widerständen aus polykristallinem Silizium.

Info

Publication number
DE3885121D1
DE3885121D1 DE88301351T DE3885121T DE3885121D1 DE 3885121 D1 DE3885121 D1 DE 3885121D1 DE 88301351 T DE88301351 T DE 88301351T DE 3885121 T DE3885121 T DE 3885121T DE 3885121 D1 DE3885121 D1 DE 3885121D1
Authority
DE
Germany
Prior art keywords
manufacture
polycrystalline silicon
silicon resistors
resistors
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88301351T
Other languages
English (en)
Other versions
DE3885121T2 (de
Inventor
Ashok K Kapoor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE3885121D1 publication Critical patent/DE3885121D1/de
Application granted granted Critical
Publication of DE3885121T2 publication Critical patent/DE3885121T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/136—Resistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/934—Sheet resistance, i.e. dopant parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE3885121T 1987-02-20 1988-02-18 Herstellung von Widerständen aus polykristallinem Silizium. Expired - Fee Related DE3885121T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/017,388 US4762801A (en) 1987-02-20 1987-02-20 Method of fabricating polycrystalline silicon resistors having desired temperature coefficients

Publications (2)

Publication Number Publication Date
DE3885121D1 true DE3885121D1 (de) 1993-12-02
DE3885121T2 DE3885121T2 (de) 1994-05-26

Family

ID=21782317

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3885121T Expired - Fee Related DE3885121T2 (de) 1987-02-20 1988-02-18 Herstellung von Widerständen aus polykristallinem Silizium.

Country Status (5)

Country Link
US (1) US4762801A (de)
EP (1) EP0281276B1 (de)
JP (1) JPH0777259B2 (de)
KR (1) KR910000019B1 (de)
DE (1) DE3885121T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240511A (en) * 1987-02-20 1993-08-31 National Semiconductor Corporation Lightly doped polycrystalline silicon resistor having a non-negative temperature coefficient
KR900005038B1 (ko) * 1987-07-31 1990-07-18 삼성전자 주식회사 고저항 다결정 실리콘의 제조방법
US4818711A (en) * 1987-08-28 1989-04-04 Intel Corporation High quality oxide on an ion implanted polysilicon surface
US5214497A (en) * 1988-05-25 1993-05-25 Hitachi, Ltd. Polycrystalline silicon resistor for use in a semiconductor integrated circuit having a memory device
US5037766A (en) * 1988-12-06 1991-08-06 Industrial Technology Research Institute Method of fabricating a thin film polysilicon thin film transistor or resistor
US5126279A (en) * 1988-12-19 1992-06-30 Micron Technology, Inc. Single polysilicon cross-coupled resistor, six-transistor SRAM cell design technique
US5242507A (en) * 1989-04-05 1993-09-07 Boston University Impurity-induced seeding of polycrystalline semiconductors
KR910007657B1 (ko) * 1989-05-23 1991-09-30 삼성전자 주식회사 반도체 온도검출회로
US5047826A (en) * 1989-06-30 1991-09-10 Texas Instruments Incorporated Gigaohm load resistor for BICMOS process
US5457062A (en) * 1989-06-30 1995-10-10 Texas Instruments Incorporated Method for forming gigaohm load for BiCMOS process
JP3082923B2 (ja) * 1989-12-26 2000-09-04 ソニー株式会社 半導体装置の製法
JP2890601B2 (ja) * 1990-02-08 1999-05-17 株式会社デンソー 半導体センサ
US5538915A (en) * 1992-06-05 1996-07-23 The Regents Of The University Of California Process for forming synapses in neural networks and resistor therefor
JP2601136B2 (ja) * 1993-05-07 1997-04-16 日本電気株式会社 半導体装置の製造方法
JP3254072B2 (ja) * 1994-02-15 2002-02-04 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5620906A (en) 1994-02-28 1997-04-15 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device by introducing hydrogen ions
JP3254885B2 (ja) * 1994-03-22 2002-02-12 双葉電子工業株式会社 抵抗体の製造方法
US5872381A (en) * 1996-05-23 1999-02-16 Sony Corporation Semiconductor device and its manufacturing method
JPH10303372A (ja) * 1997-01-31 1998-11-13 Sanyo Electric Co Ltd 半導体集積回路およびその製造方法
US6114744A (en) * 1997-03-14 2000-09-05 Sanyo Electric Company Semiconductor integration device and fabrication method of the same
US6242314B1 (en) 1998-09-28 2001-06-05 Taiwan Semiconductor Manufacturing Company Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor
US6255185B1 (en) 1999-05-19 2001-07-03 International Business Machines Corporation Two step anneal for controlling resistor tolerance
US6472232B1 (en) 2000-02-22 2002-10-29 International Business Machines Corporation Semiconductor temperature monitor
JP4222841B2 (ja) * 2003-01-15 2009-02-12 三洋電機株式会社 半導体装置の製造方法
DE10322588B4 (de) * 2003-05-20 2006-10-05 Infineon Technologies Ag Verfahren zum Herstellen einer Widerstandsschicht
CN100389489C (zh) * 2003-12-30 2008-05-21 中芯国际集成电路制造(上海)有限公司 利用注入晶片的注入机的低能量剂量监测
US8957511B2 (en) 2005-08-22 2015-02-17 Madhukar B. Vora Apparatus and methods for high-density chip connectivity
US7745301B2 (en) 2005-08-22 2010-06-29 Terapede, Llc Methods and apparatus for high-density chip connectivity

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4411708A (en) * 1980-08-25 1983-10-25 Trw Inc. Method of making precision doped polysilicon vertical ballast resistors by multiple implantations
JPS57201061A (en) * 1981-06-05 1982-12-09 Toshiba Corp Manufacture of thin semiconductor film resistor
US4467519A (en) * 1982-04-01 1984-08-28 International Business Machines Corporation Process for fabricating polycrystalline silicon film resistors
JPS59155121A (ja) * 1983-02-24 1984-09-04 Toshiba Corp 半導体薄膜の製造方法
US4579600A (en) * 1983-06-17 1986-04-01 Texas Instruments Incorporated Method of making zero temperature coefficient of resistance resistors
JPS60127755A (ja) * 1983-12-15 1985-07-08 Sony Corp 半導体装置の製法
JPS60130844A (ja) * 1983-12-20 1985-07-12 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0281276B1 (de) 1993-10-27
KR910000019B1 (ko) 1991-01-19
KR880010441A (ko) 1988-10-08
JPH0777259B2 (ja) 1995-08-16
US4762801A (en) 1988-08-09
EP0281276A1 (de) 1988-09-07
DE3885121T2 (de) 1994-05-26
JPS6446966A (en) 1989-02-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee