DE3852860T2 - Speicher in einer integrierten Schaltung. - Google Patents

Speicher in einer integrierten Schaltung.

Info

Publication number
DE3852860T2
DE3852860T2 DE3852860T DE3852860T DE3852860T2 DE 3852860 T2 DE3852860 T2 DE 3852860T2 DE 3852860 T DE3852860 T DE 3852860T DE 3852860 T DE3852860 T DE 3852860T DE 3852860 T2 DE3852860 T2 DE 3852860T2
Authority
DE
Germany
Prior art keywords
memory
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3852860T
Other languages
English (en)
Other versions
DE3852860D1 (de
Inventor
Albert Bergemont
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE3852860D1 publication Critical patent/DE3852860D1/de
Application granted granted Critical
Publication of DE3852860T2 publication Critical patent/DE3852860T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE3852860T 1987-10-09 1988-09-30 Speicher in einer integrierten Schaltung. Expired - Fee Related DE3852860T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8713951A FR2621737B1 (fr) 1987-10-09 1987-10-09 Memoire en circuit integre

Publications (2)

Publication Number Publication Date
DE3852860D1 DE3852860D1 (de) 1995-03-09
DE3852860T2 true DE3852860T2 (de) 1995-06-01

Family

ID=9355657

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3852860T Expired - Fee Related DE3852860T2 (de) 1987-10-09 1988-09-30 Speicher in einer integrierten Schaltung.

Country Status (5)

Country Link
EP (1) EP0313427B1 (de)
JP (1) JPH02373A (de)
KR (1) KR890007427A (de)
DE (1) DE3852860T2 (de)
FR (1) FR2621737B1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091327A (en) * 1990-06-28 1992-02-25 National Semiconductor Corporation Fabrication of a high density stacked gate eprom split cell with bit line reach-through and interruption immunity
US5222040A (en) * 1990-12-11 1993-06-22 Nexcom Technology, Inc. Single transistor eeprom memory cell
JPH06120514A (ja) * 1991-01-17 1994-04-28 Texas Instr Inc <Ti> 不揮発性メモリ・セル構造体とその製造法
US5345418A (en) * 1991-01-24 1994-09-06 Nexcom Technology, Inc. Single transistor EEPROM architecture
TW417256B (en) 1997-01-31 2001-01-01 Seiko Epson Corp Semiconductor MOS device and its manufacturing method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5464480A (en) * 1977-10-31 1979-05-24 Nec Corp Semiconductor device
SE7907193L (sv) * 1978-09-28 1980-03-29 Rca Corp Bestendigt minne
US4377818A (en) * 1978-11-02 1983-03-22 Texas Instruments Incorporated High density electrically programmable ROM
US4375087C1 (en) * 1980-04-09 2002-01-01 Hughes Aircraft Co Electrically erasable programmable read-only memory
JPS5728364A (en) * 1980-07-28 1982-02-16 Fujitsu Ltd Semiconductor memory device
JPS60170264A (ja) * 1984-02-15 1985-09-03 Toshiba Corp 半導体記憶装置
US4639893A (en) * 1984-05-15 1987-01-27 Wafer Scale Integration, Inc. Self-aligned split gate EPROM
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
JPS61294869A (ja) * 1985-06-21 1986-12-25 Toshiba Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
DE3852860D1 (de) 1995-03-09
FR2621737B1 (fr) 1991-04-05
FR2621737A1 (fr) 1989-04-14
KR890007427A (ko) 1989-06-19
JPH02373A (ja) 1990-01-05
EP0313427B1 (de) 1995-01-25
EP0313427A1 (de) 1989-04-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee