DE3830131A1 - Flip-chip-halbleitereinrichtung - Google Patents

Flip-chip-halbleitereinrichtung

Info

Publication number
DE3830131A1
DE3830131A1 DE3830131A DE3830131A DE3830131A1 DE 3830131 A1 DE3830131 A1 DE 3830131A1 DE 3830131 A DE3830131 A DE 3830131A DE 3830131 A DE3830131 A DE 3830131A DE 3830131 A1 DE3830131 A1 DE 3830131A1
Authority
DE
Germany
Prior art keywords
connection
electrode
layer
semiconductor device
active region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3830131A
Other languages
German (de)
English (en)
Other versions
DE3830131C2 (https=
Inventor
Shigeru Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3830131A1 publication Critical patent/DE3830131A1/de
Application granted granted Critical
Publication of DE3830131C2 publication Critical patent/DE3830131C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4405—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE3830131A 1987-10-02 1988-09-05 Flip-chip-halbleitereinrichtung Granted DE3830131A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62250351A JPH0193149A (ja) 1987-10-02 1987-10-02 半導体装置

Publications (2)

Publication Number Publication Date
DE3830131A1 true DE3830131A1 (de) 1989-04-20
DE3830131C2 DE3830131C2 (https=) 1993-08-12

Family

ID=17206624

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3830131A Granted DE3830131A1 (de) 1987-10-02 1988-09-05 Flip-chip-halbleitereinrichtung

Country Status (2)

Country Link
JP (1) JPH0193149A (https=)
DE (1) DE3830131A1 (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4019848A1 (de) * 1989-10-17 1991-04-25 Mitsubishi Electric Corp Halbleitereinrichtung mit einer eine pufferschicht aufweisenden anschlussflaeche
EP0586890A3 (en) * 1992-08-31 1994-06-08 Ibm Etching processes for avoiding edge stress in semiconductor chip solder bumps
WO1996002071A1 (en) * 1994-07-10 1996-01-25 Shellcase Ltd. Packaged integrated circuit
US5716759A (en) * 1993-09-02 1998-02-10 Shellcase Ltd. Method and apparatus for producing integrated circuit devices
US6040235A (en) * 1994-01-17 2000-03-21 Shellcase Ltd. Methods and apparatus for producing integrated circuit devices
EP1596435A3 (en) * 2004-05-11 2008-10-08 Ricoh Company A pattern form object and a manufacturing method thereof
US12498641B2 (en) * 2020-03-02 2025-12-16 Inpria Corporation Process environment for inorganic resist patterning

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4896487B2 (ja) * 2005-10-17 2012-03-14 日本碍子株式会社 誘電体デバイスの製造方法、及び誘電体デバイス
JP2008114795A (ja) * 2006-11-07 2008-05-22 Mazda Motor Corp カーテンエアバッグ装置を備えた車両構造

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1513077A (en) * 1975-10-24 1978-06-07 Ibm Conductive stripes for electronic components
DE3346239A1 (de) * 1982-12-21 1984-07-05 Tokyo Shibaura Denki K.K., Kawasaki Beschaltungsmaterial fuer eine halbleitervorrichtung und verfahren zur bildung eines beschaltungsmusters

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5688359A (en) * 1979-12-21 1981-07-17 Toshiba Corp Semiconductor device and manufacture thereof
JPS6288342A (ja) * 1985-10-15 1987-04-22 Fujitsu Ltd 積層強化型配線層の構造とその形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1513077A (en) * 1975-10-24 1978-06-07 Ibm Conductive stripes for electronic components
DE3346239A1 (de) * 1982-12-21 1984-07-05 Tokyo Shibaura Denki K.K., Kawasaki Beschaltungsmaterial fuer eine halbleitervorrichtung und verfahren zur bildung eines beschaltungsmusters

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Fried, L.J. et.al.: A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connection. In: IBM J. Res. Develop., Bd. 26, Nr. 3, Mai 1982, S. 362-371 *
JP-Abstract der 61-156837 (A) *
JP-Abstract der 62-88342(A) *
Kawanobe, T. et.al.: Solder Bump Fabrication by Electrochemical Method for Flipchip Interconnection. In: CH 1671-7/81/0000-0149, IEEE 1981, S. 149-155 *
Magerlein, J.H. und Murakami, M.: Control of Thin Film Grain Size by Lithographic Methods. In: IBM TDB, Bd. 24, Nr. 4, Sept. 1981, S. 1974-75 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4019848A1 (de) * 1989-10-17 1991-04-25 Mitsubishi Electric Corp Halbleitereinrichtung mit einer eine pufferschicht aufweisenden anschlussflaeche
EP0586890A3 (en) * 1992-08-31 1994-06-08 Ibm Etching processes for avoiding edge stress in semiconductor chip solder bumps
US5716759A (en) * 1993-09-02 1998-02-10 Shellcase Ltd. Method and apparatus for producing integrated circuit devices
US6040235A (en) * 1994-01-17 2000-03-21 Shellcase Ltd. Methods and apparatus for producing integrated circuit devices
WO1996002071A1 (en) * 1994-07-10 1996-01-25 Shellcase Ltd. Packaged integrated circuit
US6022758A (en) * 1994-07-10 2000-02-08 Shellcase Ltd. Process for manufacturing solder leads on a semiconductor device package
EP1596435A3 (en) * 2004-05-11 2008-10-08 Ricoh Company A pattern form object and a manufacturing method thereof
US12498641B2 (en) * 2020-03-02 2025-12-16 Inpria Corporation Process environment for inorganic resist patterning

Also Published As

Publication number Publication date
DE3830131C2 (https=) 1993-08-12
JPH0193149A (ja) 1989-04-12

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee