DE3827959C2 - - Google Patents

Info

Publication number
DE3827959C2
DE3827959C2 DE19883827959 DE3827959A DE3827959C2 DE 3827959 C2 DE3827959 C2 DE 3827959C2 DE 19883827959 DE19883827959 DE 19883827959 DE 3827959 A DE3827959 A DE 3827959A DE 3827959 C2 DE3827959 C2 DE 3827959C2
Authority
DE
Germany
Prior art keywords
test
pin
commands
test device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19883827959
Other languages
German (de)
English (en)
Other versions
DE3827959A1 (de
Inventor
Antun Dipl.-Ing. 8000 Muenchen De Vuksic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19883827959 priority Critical patent/DE3827959A1/de
Publication of DE3827959A1 publication Critical patent/DE3827959A1/de
Application granted granted Critical
Publication of DE3827959C2 publication Critical patent/DE3827959C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31724—Test controller, e.g. BIST state machine
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE19883827959 1988-08-17 1988-08-17 Testgeraet zur funktionspruefung von elektroischen bausteinen Granted DE3827959A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19883827959 DE3827959A1 (de) 1988-08-17 1988-08-17 Testgeraet zur funktionspruefung von elektroischen bausteinen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19883827959 DE3827959A1 (de) 1988-08-17 1988-08-17 Testgeraet zur funktionspruefung von elektroischen bausteinen

Publications (2)

Publication Number Publication Date
DE3827959A1 DE3827959A1 (de) 1990-02-22
DE3827959C2 true DE3827959C2 (enrdf_load_stackoverflow) 1991-10-24

Family

ID=6361063

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883827959 Granted DE3827959A1 (de) 1988-08-17 1988-08-17 Testgeraet zur funktionspruefung von elektroischen bausteinen

Country Status (1)

Country Link
DE (1) DE3827959A1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4442636A1 (de) * 1994-02-14 1995-08-24 Hewlett Packard Co Bezahlung-pro-Anwendung-Zugriff auf vielfache elektronische Testfähigkeiten und Testbetriebsmittel

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2038295A1 (en) * 1990-03-16 1991-09-17 Brian Jerrold Arkin High speed fail processor
DE4101950C2 (de) * 1991-01-21 1998-07-09 Bally Wulff Automaten Gmbh Anordnung zur Pfadansteuerung in einem Service-Baum bei Münzspielautomaten

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4639919A (en) * 1983-12-19 1987-01-27 International Business Machines Corporation Distributed pattern generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4442636A1 (de) * 1994-02-14 1995-08-24 Hewlett Packard Co Bezahlung-pro-Anwendung-Zugriff auf vielfache elektronische Testfähigkeiten und Testbetriebsmittel

Also Published As

Publication number Publication date
DE3827959A1 (de) 1990-02-22

Similar Documents

Publication Publication Date Title
DE4305442C2 (de) Verfahren und Vorrichtung zum Erzeugen eines Testvektors
DE2918053C2 (enrdf_load_stackoverflow)
DE69124170T2 (de) Automatisches Prüfausrüstungssystem, das eine Stiftscheibenarchitektur verwendet
DE69019402T2 (de) Prüfverfahren und -gerät für integrierte Schaltungen.
DE69100204T2 (de) Einrichtung zur Erzeugung von Testsignalen.
DE2439577C2 (de) Verfahren zum Prüfen von hochintegrierten logischen Schaltungen und Einrichtung zur Durchführung des Verfahrens
DE3606650A1 (de) Hardware logik-simulator
DE68923086T2 (de) Verfahren zum Testen von hierarchisch organisierten integrierten Schaltungen und integrierte Schaltungen, geeignet für einen solchen Test.
DE2311034A1 (de) Verfahren zum pruefen einer schaltungsanordnung
DE2658611A1 (de) Vorrichtung zur erzeugung und zum empfang von digitalwoertern
EP0038947A2 (de) Programmierbare logische Anordnung
DE3515802C2 (enrdf_load_stackoverflow)
DE3900248C2 (de) Verfahren zur schnellen Ablaufsteuerung digitaler Testmuster und Vorrichtung zur Durchführung des Verfahrens
DE3689414T2 (de) Automatisches Prüfsystem mit "wahrem Prüfer-per-Anschluss" -Architektur.
DE1927549A1 (de) Fehlerpruefeinrichtung in elektronischen Datenverarbeitungsanlagen
DE19807237C2 (de) Halbleiterbauelement-Testgerät
DE3237365C2 (enrdf_load_stackoverflow)
DE3850547T2 (de) Speicher mit eingebautem Logik-LSI und Verfahren zum LSI-Prüfen.
DE3827959C2 (enrdf_load_stackoverflow)
DE3024153A1 (de) Speicher-subsystem
DE3317593A1 (de) Pruefspeicherarchitektur
DE69122001T2 (de) Integrierte Schaltung mit einer Standardzelle, einer Anwendungszelle und einer Prüfzelle
DE1234054B (de) Byte-Umsetzer
DE3532484A1 (de) Anordnung zur modelldarstellung einer physikalischen elektrischen komponente in einer elektrischen logiksimulation
DE3885935T2 (de) Digitaler In-Circuit-Prüfer mit Kanalspeicherlöschschutz.

Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee