DE3808193A1 - Computersystem mit gedruckten schaltungskarten fuer erweiterungsschlitze - Google Patents

Computersystem mit gedruckten schaltungskarten fuer erweiterungsschlitze

Info

Publication number
DE3808193A1
DE3808193A1 DE3808193A DE3808193A DE3808193A1 DE 3808193 A1 DE3808193 A1 DE 3808193A1 DE 3808193 A DE3808193 A DE 3808193A DE 3808193 A DE3808193 A DE 3808193A DE 3808193 A1 DE3808193 A1 DE 3808193A1
Authority
DE
Germany
Prior art keywords
memory
cpu
slot
card
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE3808193A
Other languages
German (de)
English (en)
Inventor
Jonathan Fitch
Ronald Hochsprung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/025,500 external-priority patent/US4905182A/en
Priority claimed from US07/025,499 external-priority patent/US4931923A/en
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of DE3808193A1 publication Critical patent/DE3808193A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Memory System (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Multi Processors (AREA)
DE3808193A 1987-03-13 1988-03-11 Computersystem mit gedruckten schaltungskarten fuer erweiterungsschlitze Ceased DE3808193A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/025,500 US4905182A (en) 1987-03-13 1987-03-13 Self-configuring memory management system with on card circuitry for non-contentious allocation of reserved memory space among expansion cards
US07/025,499 US4931923A (en) 1987-03-13 1987-03-13 Computer system for automatically reconfigurating memory space to avoid overlaps of memory reserved for expansion slots

Publications (1)

Publication Number Publication Date
DE3808193A1 true DE3808193A1 (de) 1988-09-22

Family

ID=26699830

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3808193A Ceased DE3808193A1 (de) 1987-03-13 1988-03-11 Computersystem mit gedruckten schaltungskarten fuer erweiterungsschlitze

Country Status (7)

Country Link
JP (1) JPS63314657A (ko)
KR (1) KR950014182B1 (ko)
CN (1) CN1017007B (ko)
AU (2) AU616171B2 (ko)
DE (1) DE3808193A1 (ko)
FR (1) FR2612314B1 (ko)
IL (1) IL85518A0 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2203869B (en) * 1987-04-17 1991-10-23 Apple Computer Computer resource configuration method and apparatus
CN101321250B (zh) * 2008-07-03 2010-06-02 四川长虹电器股份有限公司 一种电视机重要数据存储方法
US10146253B2 (en) * 2016-03-10 2018-12-04 Epro Gmbh Combined slot and backplane identification

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2060961A (en) * 1979-10-10 1981-05-07 Magnuson Computer Systems Inc Data processing system having memory modules with distributed address information

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675083A (en) * 1970-09-14 1972-07-04 Digital Equipment Corp Universal bus arrangement for data processing systems
US4373181A (en) * 1980-07-30 1983-02-08 Chisholm Douglas R Dynamic device address assignment mechanism for a data processing system
GB2101370A (en) * 1981-06-26 1983-01-12 Philips Electronic Associated Digital data apparatus with memory interrogation
GB2103397A (en) * 1981-07-31 1983-02-16 Philips Electronic Associated Digital data aparatus with memory selection
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2060961A (en) * 1979-10-10 1981-05-07 Magnuson Computer Systems Inc Data processing system having memory modules with distributed address information

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MITCHELL, H.J.: 32-Bit Microprocessors, Collins Professional and Technical Books 1986, S. 158 *

Also Published As

Publication number Publication date
CN88101358A (zh) 1988-09-21
AU1276988A (en) 1988-09-15
JPS63314657A (ja) 1988-12-22
KR950014182B1 (ko) 1995-11-22
FR2612314A1 (fr) 1988-09-16
CN1017007B (zh) 1992-06-10
AU640850B2 (en) 1993-09-02
IL85518A0 (en) 1988-08-31
FR2612314B1 (fr) 1991-11-22
KR880011668A (ko) 1988-10-29
AU616171B2 (en) 1991-10-24
AU1035492A (en) 1992-03-12

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: G06F 12/06

8131 Rejection