DE3788453T2 - Komplementäres vertikales bipolares Transistorpaar mit flachem Übergang. - Google Patents

Komplementäres vertikales bipolares Transistorpaar mit flachem Übergang.

Info

Publication number
DE3788453T2
DE3788453T2 DE3788453T DE3788453T DE3788453T2 DE 3788453 T2 DE3788453 T2 DE 3788453T2 DE 3788453 T DE3788453 T DE 3788453T DE 3788453 T DE3788453 T DE 3788453T DE 3788453 T2 DE3788453 T2 DE 3788453T2
Authority
DE
Germany
Prior art keywords
pnp
transistor
region
collector
npn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3788453T
Other languages
German (de)
English (en)
Other versions
DE3788453D1 (de
Inventor
George Richard Goth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3788453D1 publication Critical patent/DE3788453D1/de
Publication of DE3788453T2 publication Critical patent/DE3788453T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
DE3788453T 1986-04-28 1987-03-06 Komplementäres vertikales bipolares Transistorpaar mit flachem Übergang. Expired - Fee Related DE3788453T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/856,521 US4719185A (en) 1986-04-28 1986-04-28 Method of making shallow junction complementary vertical bipolar transistor pair

Publications (2)

Publication Number Publication Date
DE3788453D1 DE3788453D1 (de) 1994-01-27
DE3788453T2 true DE3788453T2 (de) 1994-06-23

Family

ID=25323834

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3788453T Expired - Fee Related DE3788453T2 (de) 1986-04-28 1987-03-06 Komplementäres vertikales bipolares Transistorpaar mit flachem Übergang.

Country Status (5)

Country Link
US (1) US4719185A (enExample)
EP (1) EP0243622B1 (enExample)
JP (1) JPS62256465A (enExample)
CA (1) CA1243421A (enExample)
DE (1) DE3788453T2 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051805A (en) * 1987-07-15 1991-09-24 Rockwell International Corporation Sub-micron bipolar devices with sub-micron contacts
US5055418A (en) * 1987-07-29 1991-10-08 National Semiconductor Corporation Process for fabricating complementary contactless vertical bipolar transistors
US5518937A (en) * 1988-03-11 1996-05-21 Fujitsu Limited Semiconductor device having a region doped to a level exceeding the solubility limit
US5270224A (en) * 1988-03-11 1993-12-14 Fujitsu Limited Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit
US4900689A (en) * 1988-12-08 1990-02-13 Harris Corporation Method of fabrication of isolated islands for complementary bipolar devices
US4910160A (en) * 1989-06-06 1990-03-20 National Semiconductor Corporation High voltage complementary NPN/PNP process
US5206182A (en) * 1989-06-08 1993-04-27 United Technologies Corporation Trench isolation process
US4997775A (en) * 1990-02-26 1991-03-05 Cook Robert K Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor
US5151378A (en) * 1991-06-18 1992-09-29 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process
WO1993016494A1 (en) * 1992-01-31 1993-08-19 Analog Devices, Inc. Complementary bipolar polysilicon emitter devices
KR950034673A (ko) * 1994-04-20 1995-12-28 윌리엄 이. 힐러 로우-케이 유전체를 사용하는 트랜지스터 분리 방법 및 장치
US5447884A (en) * 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
US6649477B2 (en) * 2001-10-04 2003-11-18 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US7736976B2 (en) * 2001-10-04 2010-06-15 Vishay General Semiconductor Llc Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US7226835B2 (en) * 2001-12-28 2007-06-05 Texas Instruments Incorporated Versatile system for optimizing current gain in bipolar transistor structures
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
JP3967193B2 (ja) * 2002-05-21 2007-08-29 スパンション エルエルシー 不揮発性半導体記憶装置及びその製造方法
DE10358047A1 (de) * 2003-12-05 2005-06-30 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Komplementäre Bipolar-Halbleitervorrichtung
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough
US8766235B2 (en) * 2012-03-08 2014-07-01 Micron Technology, Inc. Bipolar junction transistors and memory arrays
JP6333483B2 (ja) 2014-12-24 2018-05-30 スリーエム イノベイティブ プロパティズ カンパニー リボン及びストランドを有するポリマーネット、及びその製造方法
US10134721B2 (en) * 2016-08-01 2018-11-20 Texas Instruments Incorporated Variable holding voltage silicon controlled rectifier using separate and distinct bipolars

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3930909A (en) * 1966-10-21 1976-01-06 U.S. Philips Corporation Method of manufacturing a semiconductor device utilizing simultaneous outdiffusion during epitaxial growth
US3617827A (en) * 1970-03-30 1971-11-02 Albert Schmitz Semiconductor device with complementary transistors
US3730786A (en) * 1970-09-03 1973-05-01 Ibm Performance matched complementary pair transistors
IT946150B (it) * 1971-12-15 1973-05-21 Ates Componenti Elettron Perfezionamento al processo plana re epistssiale per la produzione di circuiti integrati lineari di potenza
JPS5017180A (enExample) * 1973-06-13 1975-02-22
US4412376A (en) * 1979-03-30 1983-11-01 Ibm Corporation Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation
JPS55156366A (en) * 1979-05-24 1980-12-05 Toshiba Corp Semiconductor device
US4485552A (en) * 1980-01-18 1984-12-04 International Business Machines Corporation Complementary transistor structure and method for manufacture
US4381953A (en) * 1980-03-24 1983-05-03 International Business Machines Corporation Polysilicon-base self-aligned bipolar transistor process
US4339767A (en) * 1980-05-05 1982-07-13 International Business Machines Corporation High performance PNP and NPN transistor structure
US4553318A (en) * 1983-05-02 1985-11-19 Rca Corporation Method of making integrated PNP and NPN bipolar transistors and junction field effect transistor
JPS60194558A (ja) * 1984-03-16 1985-10-03 Hitachi Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS62256465A (ja) 1987-11-09
EP0243622B1 (en) 1993-12-15
CA1243421A (en) 1988-10-18
EP0243622A3 (en) 1990-11-28
DE3788453D1 (de) 1994-01-27
EP0243622A2 (en) 1987-11-04
US4719185A (en) 1988-01-12
JPH0583195B2 (enExample) 1993-11-25

Similar Documents

Publication Publication Date Title
DE3788453T2 (de) Komplementäres vertikales bipolares Transistorpaar mit flachem Übergang.
DE69030415T2 (de) Verfahren zur Herstellung eines DMOS Transistors
EP0036634B1 (de) Verfahren zur Herstellung einer bipolaren Transistorstruktur
EP0032550B1 (de) Verfahren zur Herstellung einer bipolaren, vertikalen PNP-Transistorstruktur
DE3105118C2 (de) Verfahren zur Herstellung einer integrierten Schaltung mit komplementären bipolaren Transistoren und komplementären Isolierschicht-Gate-Feldeffekttransistoren auf einem gemeinsamen Substrat
EP0219641B1 (de) Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
DE69223670T2 (de) Halbleiteranordnung mit einem Heteroübergang-Bipolartransistor und Verfahren zu seiner Herstellung
DE2711562A1 (de) Halbleiteranordnung und deren herstellung
DE2056220A1 (de) Verfahren zur Herstellung einer elektn sehen Anordnung, und Anordnung hergestellt nach dem Verfahren
DE69509211T2 (de) Struktur und herstellung bipolarer transistoren
DE19909993A1 (de) Verfahren zum Bilden von Bipolartransistoren mit selbstausrichtender epitaktischer Basis
DE3850847T2 (de) Selbstjustierter Polysiliziumemitter und Kontaktstruktur für Hochleistungsbipolartransistor.
EP0006510B1 (de) Verfahren zum Erzeugen aneinander grenzender, unterschiedlich dotierter Siliciumbereiche
DE4444776C2 (de) Verfahren zur Herstellung eines Bipolartransistors mit einer selbstjustierenden vertikalen Struktur
EP0007923A1 (de) Verfahren zur Herstellung eines doppeltdiffundierten, lateralen Transistors und eines mit diesem integrierten komplementären vertikalen Transistors
DE3884665T2 (de) Hochleistungstransistor mit Seitenwandemitter.
EP1625614B1 (de) Verfahren zur herstellung eines bipolartransistors
DE69425748T2 (de) Transistoren und Verfahren zu deren Herstellung
DE69132468T2 (de) Selbst ausrichtende Kollektor-Implantation für bipolare Transistoren
DE19615324A1 (de) Verfahren zum Herstellen eines vertikalen bipolaren Transistors
DE69216304T2 (de) Verfahren zum Herstellen eines selbst-ausrichtenden, planaren, monolithischen integrierten Schaltkreises mit vertikalen Transistoren
DE3022565A1 (de) Halbleiteranordnung
DE3781573T2 (de) Selbstausrichtender kontakt auf einer diffundierten zone des p-typs.
DE10352765B4 (de) Hetero-Bipolartransistor mit einem schmalen Dotierungsprofil
DE69030225T2 (de) Verfahren zur Herstellung von BiMOS-Schaltungen mit hoher Leistung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee