DE3788032T2 - Struktur zum Wiederordnen von Bits auf dem Chip. - Google Patents

Struktur zum Wiederordnen von Bits auf dem Chip.

Info

Publication number
DE3788032T2
DE3788032T2 DE87110153T DE3788032T DE3788032T2 DE 3788032 T2 DE3788032 T2 DE 3788032T2 DE 87110153 T DE87110153 T DE 87110153T DE 3788032 T DE3788032 T DE 3788032T DE 3788032 T2 DE3788032 T2 DE 3788032T2
Authority
DE
Germany
Prior art keywords
bit
register
gate
data
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87110153T
Other languages
German (de)
English (en)
Other versions
DE3788032D1 (de
Inventor
Frederick John Aichelmann
Bruce Engle Bachman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3788032D1 publication Critical patent/DE3788032D1/de
Application granted granted Critical
Publication of DE3788032T2 publication Critical patent/DE3788032T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE87110153T 1986-09-15 1987-07-14 Struktur zum Wiederordnen von Bits auf dem Chip. Expired - Fee Related DE3788032T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/907,192 US4845664A (en) 1986-09-15 1986-09-15 On-chip bit reordering structure

Publications (2)

Publication Number Publication Date
DE3788032D1 DE3788032D1 (de) 1993-12-09
DE3788032T2 true DE3788032T2 (de) 1994-05-11

Family

ID=25423670

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87110153T Expired - Fee Related DE3788032T2 (de) 1986-09-15 1987-07-14 Struktur zum Wiederordnen von Bits auf dem Chip.

Country Status (4)

Country Link
US (1) US4845664A (forum.php)
EP (1) EP0263924B1 (forum.php)
JP (1) JPS6373447A (forum.php)
DE (1) DE3788032T2 (forum.php)

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US6112287A (en) 1993-03-01 2000-08-29 Busless Computers Sarl Shared memory multiprocessor system using a set of serial links as processors-memory switch
US5442770A (en) * 1989-01-24 1995-08-15 Nec Electronics, Inc. Triple port cache memory
US5187783A (en) * 1989-03-15 1993-02-16 Micral, Inc. Controller for direct memory access
US5233702A (en) * 1989-08-07 1993-08-03 International Business Machines Corporation Cache miss facility with stored sequences for data fetching
US5036495A (en) * 1989-12-28 1991-07-30 International Business Machines Corp. Multiple mode-set for IC chip
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
US5280601A (en) * 1990-03-02 1994-01-18 Seagate Technology, Inc. Buffer memory control system for a magnetic disc controller
US5121354A (en) * 1990-03-12 1992-06-09 International Business Machines Corp. Random access memory with access on bit boundaries
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
US5995443A (en) * 1990-04-18 1999-11-30 Rambus Inc. Synchronous memory device
JPH0831276B2 (ja) * 1990-06-15 1996-03-27 松下電器産業株式会社 半導体メモリ
US5278967A (en) * 1990-08-31 1994-01-11 International Business Machines Corporation System for providing gapless data transfer from page-mode dynamic random access memories
US5321697A (en) * 1992-05-28 1994-06-14 Cray Research, Inc. Solid state storage device
US5631935A (en) * 1993-05-06 1997-05-20 Run-Rad Unlimited Networking, Ltd. Method and apparatus for governing information transfer using an efficient transport protocol
US5680642A (en) * 1993-06-25 1997-10-21 At&T Global Information Solutions Company Method and apparatus for pseudo-aligned transfers of data to memory wherein a re-alignment is performed based on the data byte control header
JP3251421B2 (ja) * 1994-04-11 2002-01-28 株式会社日立製作所 半導体集積回路
JP3177094B2 (ja) * 1994-05-31 2001-06-18 富士通株式会社 半導体記憶装置
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US5802581A (en) * 1995-12-22 1998-09-01 Cirrus Logic, Inc. SDRAM memory controller with multiple arbitration points during a memory cycle
US6230245B1 (en) 1997-02-11 2001-05-08 Micron Technology, Inc. Method and apparatus for generating a variable sequence of memory device command signals
US6175894B1 (en) 1997-03-05 2001-01-16 Micron Technology, Inc. Memory device command buffer apparatus and method and memory devices and computer systems using same
US5996043A (en) 1997-06-13 1999-11-30 Micron Technology, Inc. Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US6484244B1 (en) 1997-06-17 2002-11-19 Micron Technology, Inc. Method and system for storing and processing multiple memory commands
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US5878059A (en) * 1997-09-24 1999-03-02 Emc Corporation Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory
WO1999019805A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6401167B1 (en) * 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6202119B1 (en) 1997-12-19 2001-03-13 Micron Technology, Inc. Method and system for processing pipelined memory commands
US6477143B1 (en) 1998-01-25 2002-11-05 Dror Ginossar Method and apparatus for packet network congestion avoidance and control
US6175905B1 (en) 1998-07-30 2001-01-16 Micron Technology, Inc. Method and system for bypassing pipelines in a pipelined memory command generator
US6178488B1 (en) 1998-08-27 2001-01-23 Micron Technology, Inc. Method and apparatus for processing pipelined memory commands
US6304992B1 (en) 1998-09-24 2001-10-16 Sun Microsystems, Inc. Technique for correcting single-bit errors in caches with sub-block parity bits
US6282686B1 (en) * 1998-09-24 2001-08-28 Sun Microsystems, Inc. Technique for sharing parity over multiple single-error correcting code words
US6301680B1 (en) 1998-09-24 2001-10-09 Sun Microsystems, Inc. Technique for correcting single-bit errors and detecting paired double-bit errors
WO2000074058A1 (fr) * 1999-05-28 2000-12-07 Hitachi, Ltd. Stockage, procede de stockage et systeme de traitement de donnees
US6574746B1 (en) 1999-07-02 2003-06-03 Sun Microsystems, Inc. System and method for improving multi-bit error protection in computer memory systems
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6622232B2 (en) * 2001-05-18 2003-09-16 Intel Corporation Apparatus and method for performing non-aligned memory accesses
US7149824B2 (en) * 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
JP3984206B2 (ja) * 2003-09-02 2007-10-03 株式会社東芝 マイクロプロセッサー及び映像音声システム
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7366823B2 (en) * 2005-05-11 2008-04-29 Broadcom Corporation Method and system for memory access
US7478307B1 (en) 2005-05-19 2009-01-13 Sun Microsystems, Inc. Method for improving un-correctable errors in a computer system
JP2009070502A (ja) * 2007-09-14 2009-04-02 Oki Electric Ind Co Ltd 半導体メモリ装置におけるデータ読み出し方法及び半導体メモリ装置
US20160371211A1 (en) * 2015-06-16 2016-12-22 Apple Inc. Bus-bit-order ascertainment
US9887840B2 (en) 2015-09-29 2018-02-06 International Business Machines Corporation Scrambling bit transmissions

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Publication number Priority date Publication date Assignee Title
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US4406013A (en) * 1980-10-01 1983-09-20 Intel Corporation Multiple bit output dynamic random-access memory
US4453237A (en) * 1980-10-01 1984-06-05 Intel Corporation Multiple bit output dynamic random-access memory
NL8200207A (nl) * 1982-01-21 1983-08-16 Philips Nv Werkwijze met foutkorrektie voor het overdragen van blokken databits, een inrichting voor het uitvoeren van een dergelijke werkwijze, een dekodeur voor gebruik bij een dergelijke werkwijze, en een inrichting bevattende een dergelijke dekodeur.
JPS58149548A (ja) * 1982-03-02 1983-09-05 Hitachi Ltd メモリ制御方式
US4483001A (en) * 1982-06-16 1984-11-13 International Business Machines Corporation Online realignment of memory faults
US4667308A (en) * 1982-07-21 1987-05-19 Marconi Avionics Limited Multi-dimensional-access memory system with combined data rotation and multiplexing
US4484308A (en) * 1982-09-23 1984-11-20 Motorola, Inc. Serial data mode circuit for a memory
US4513372A (en) * 1982-11-15 1985-04-23 Data General Corporation Universal memory
JPS59104791A (ja) * 1982-12-04 1984-06-16 Fujitsu Ltd 半導体記憶装置
JPS59116897A (ja) * 1982-12-23 1984-07-05 株式会社東芝 デイジタルコントロ−ラ
JPS60133599A (ja) * 1983-12-21 1985-07-16 Nec Corp 半導体メモリ装置

Also Published As

Publication number Publication date
EP0263924A3 (en) 1990-09-19
DE3788032D1 (de) 1993-12-09
EP0263924A2 (en) 1988-04-20
US4845664A (en) 1989-07-04
JPH0524596B2 (forum.php) 1993-04-08
JPS6373447A (ja) 1988-04-04
EP0263924B1 (en) 1993-11-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee