DE3736735C2 - - Google Patents

Info

Publication number
DE3736735C2
DE3736735C2 DE19873736735 DE3736735A DE3736735C2 DE 3736735 C2 DE3736735 C2 DE 3736735C2 DE 19873736735 DE19873736735 DE 19873736735 DE 3736735 A DE3736735 A DE 3736735A DE 3736735 C2 DE3736735 C2 DE 3736735C2
Authority
DE
Germany
Prior art keywords
voltage
mos transistors
source
coupled mos
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE19873736735
Other languages
German (de)
English (en)
Other versions
DE3736735A1 (de
Inventor
Eric John Buda Tex. Us Swanson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Crystal Semiconductor Corp
Original Assignee
Crystal Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Crystal Semiconductor Corp filed Critical Crystal Semiconductor Corp
Publication of DE3736735A1 publication Critical patent/DE3736735A1/de
Application granted granted Critical
Publication of DE3736735C2 publication Critical patent/DE3736735C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45479Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45766Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
    • H03F3/45771Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means using switching means
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)
DE19873736735 1986-11-12 1987-10-29 Verfahren und schaltungsanordnung zum vermindern der erholzeit eines mos-differenz-spannungs-vergleichers Granted DE3736735A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US93013186A 1986-11-12 1986-11-12

Publications (2)

Publication Number Publication Date
DE3736735A1 DE3736735A1 (de) 1988-06-01
DE3736735C2 true DE3736735C2 (enrdf_load_stackoverflow) 1990-05-03

Family

ID=25458959

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873736735 Granted DE3736735A1 (de) 1986-11-12 1987-10-29 Verfahren und schaltungsanordnung zum vermindern der erholzeit eines mos-differenz-spannungs-vergleichers

Country Status (4)

Country Link
JP (1) JPS63139416A (enrdf_load_stackoverflow)
DE (1) DE3736735A1 (enrdf_load_stackoverflow)
FR (1) FR2606565B1 (enrdf_load_stackoverflow)
GB (1) GB2198306B (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0451378A1 (en) * 1990-04-10 1991-10-16 Hewlett-Packard Limited FET amplifying circuits and methods of operation
US5272395A (en) * 1991-04-05 1993-12-21 Analog Devices, Inc. CMOS strobed comparator
WO2021200415A1 (ja) * 2020-03-30 2021-10-07 ソニーセミコンダクタソリューションズ株式会社 コンパレータ及びアナログ-デジタル変換器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028558A (en) * 1976-06-21 1977-06-07 International Business Machines Corporation High accuracy MOS comparator
US4201947A (en) * 1978-02-10 1980-05-06 Rca Corporation Long-tailed-pair connections of MOSFET's operated in sub-threshold region
US4323852A (en) * 1979-11-29 1982-04-06 University Of Iowa Research Foundation Fast recovery electrode amplifier
US4320347A (en) * 1980-10-01 1982-03-16 American Microsystems, Inc. Switched capacitor comparator
US4611130A (en) * 1984-02-13 1986-09-09 At&T Bell Laboratories Floating input comparator with precharging of input parasitic capacitors

Also Published As

Publication number Publication date
FR2606565B1 (fr) 1992-12-04
FR2606565A1 (fr) 1988-05-13
GB8726409D0 (en) 1987-12-16
GB2198306B (en) 1990-10-03
DE3736735A1 (de) 1988-06-01
GB2198306A (en) 1988-06-08
JPH0431605B2 (enrdf_load_stackoverflow) 1992-05-27
JPS63139416A (ja) 1988-06-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: GROSSE, BOCKHORNI, SCHUMACHER, 81476 MUENCHEN