DE3721929A1 - Verfahren zur herstellung hermetisch dichter elektrischer leiterbahnen in halbleiterelementen - Google Patents

Verfahren zur herstellung hermetisch dichter elektrischer leiterbahnen in halbleiterelementen

Info

Publication number
DE3721929A1
DE3721929A1 DE19873721929 DE3721929A DE3721929A1 DE 3721929 A1 DE3721929 A1 DE 3721929A1 DE 19873721929 DE19873721929 DE 19873721929 DE 3721929 A DE3721929 A DE 3721929A DE 3721929 A1 DE3721929 A1 DE 3721929A1
Authority
DE
Germany
Prior art keywords
metal
metal silicide
silicon body
bonding
sintering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873721929
Other languages
German (de)
English (en)
Other versions
DE3721929C2 (https=
Inventor
Solt Dipl Phys Katalin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Building Technologies AG
Landis and Gyr AG
Original Assignee
Landis and Gyr AG
LGZ Landis and Gyr Zug AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Landis and Gyr AG, LGZ Landis and Gyr Zug AG filed Critical Landis and Gyr AG
Publication of DE3721929A1 publication Critical patent/DE3721929A1/de
Application granted granted Critical
Publication of DE3721929C2 publication Critical patent/DE3721929C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

Landscapes

  • Pressure Sensors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Ceramic Products (AREA)
DE19873721929 1986-11-03 1987-07-02 Verfahren zur herstellung hermetisch dichter elektrischer leiterbahnen in halbleiterelementen Granted DE3721929A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH4337/86A CH671653A5 (https=) 1986-11-03 1986-11-03

Publications (2)

Publication Number Publication Date
DE3721929A1 true DE3721929A1 (de) 1988-05-11
DE3721929C2 DE3721929C2 (https=) 1990-02-08

Family

ID=4274212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873721929 Granted DE3721929A1 (de) 1986-11-03 1987-07-02 Verfahren zur herstellung hermetisch dichter elektrischer leiterbahnen in halbleiterelementen

Country Status (2)

Country Link
CH (1) CH671653A5 (https=)
DE (1) DE3721929A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999016114A1 (de) * 1997-09-23 1999-04-01 Infineon Technologies Ag Verfahren zum herstellen eines verbundteils und verbundteil

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3397278A (en) * 1965-05-06 1968-08-13 Mallory & Co Inc P R Anodic bonding

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3397278A (en) * 1965-05-06 1968-08-13 Mallory & Co Inc P R Anodic bonding

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Murarka, S.P.: Refractory Silicides for Integrated Circuits. In: J.Vac. Sci.Techn., 17(4), Juli/Aug. 1980, S. 775-792 *
Murarka,S.P.: Silicides for VLSC Applications. Academic Press, New York, London, 1983 *
Wallis, G. und Pomerantz, D.I.: Field Assisted Glass-Metal Sealing. In: J. Appl. Phys., Bd. 40, Nr. 10, Sept. 1969, S. 3946-3949 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999016114A1 (de) * 1997-09-23 1999-04-01 Infineon Technologies Ag Verfahren zum herstellen eines verbundteils und verbundteil

Also Published As

Publication number Publication date
DE3721929C2 (https=) 1990-02-08
CH671653A5 (https=) 1989-09-15

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee