DE3701599C2 - - Google Patents

Info

Publication number
DE3701599C2
DE3701599C2 DE3701599A DE3701599A DE3701599C2 DE 3701599 C2 DE3701599 C2 DE 3701599C2 DE 3701599 A DE3701599 A DE 3701599A DE 3701599 A DE3701599 A DE 3701599A DE 3701599 C2 DE3701599 C2 DE 3701599C2
Authority
DE
Germany
Prior art keywords
circuit
output
input
shift
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3701599A
Other languages
German (de)
English (en)
Other versions
DE3701599A1 (de
Inventor
Walter Robert Ormond Beach Fla. Us Steiner
Paul Andrew Daytona Beach Fla. Us Simonic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STAR TECHNOLOGIES, INC., STERLING, VA., US
Original Assignee
STAR TECHNOLOGIES Inc STERLING VA US
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STAR TECHNOLOGIES Inc STERLING VA US filed Critical STAR TECHNOLOGIES Inc STERLING VA US
Publication of DE3701599A1 publication Critical patent/DE3701599A1/de
Application granted granted Critical
Publication of DE3701599C2 publication Critical patent/DE3701599C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/10—Geometric effects
    • G06T15/40—Hidden part removal
    • G06T15/405—Hidden part removal using Z-buffer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/24—Conversion to or from floating-point codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Geometry (AREA)
  • Computer Graphics (AREA)
  • Complex Calculations (AREA)
  • Image Generation (AREA)
DE19873701599 1986-01-30 1987-01-21 Vielfunktions-arithmetisch-logische-schaltung Granted DE3701599A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/824,053 US4815021A (en) 1986-01-30 1986-01-30 Multifunction arithmetic logic unit circuit

Publications (2)

Publication Number Publication Date
DE3701599A1 DE3701599A1 (de) 1987-08-06
DE3701599C2 true DE3701599C2 (US06650917-20031118-M00005.png) 1992-01-16

Family

ID=25240489

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873701599 Granted DE3701599A1 (de) 1986-01-30 1987-01-21 Vielfunktions-arithmetisch-logische-schaltung

Country Status (5)

Country Link
US (1) US4815021A (US06650917-20031118-M00005.png)
JP (1) JPS62197823A (US06650917-20031118-M00005.png)
DE (1) DE3701599A1 (US06650917-20031118-M00005.png)
FR (1) FR2593620A1 (US06650917-20031118-M00005.png)
GB (1) GB2186105B (US06650917-20031118-M00005.png)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0776911B2 (ja) * 1988-03-23 1995-08-16 松下電器産業株式会社 浮動小数点演算装置
US5038309A (en) * 1989-09-15 1991-08-06 Sun Microsystems, Inc. Number conversion apparatus
DE3936334A1 (de) * 1989-10-30 1991-05-02 Siemens Ag Datentransfer-verfahren
JPH04290122A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd 数値表現変換装置
US5420815A (en) * 1991-10-29 1995-05-30 Advanced Micro Devices, Inc. Digital multiplication and accumulation system
DE69418646T2 (de) * 1993-06-04 2000-06-29 Sun Microsystems Inc Gleitkommaprozessor für einen hochleistungsfähigen dreidimensionalen Graphikbeschleuniger
EP0638859B1 (de) * 1993-08-09 1999-09-29 Siemens Aktiengesellschaft Signalverarbeitungseinrichtung
JP4072738B2 (ja) * 1997-08-21 2008-04-09 Ｓｍｃ株式会社 ５ポート電磁弁ボディを利用した３ポート電磁弁
US7043511B1 (en) * 2002-08-30 2006-05-09 Lattice Semiconductor Corporation Performing conditional operations in a programmable logic device
US8667045B1 (en) * 2011-05-11 2014-03-04 Altera Corporation Generalized parallel counter structures in logic devices
US9043290B2 (en) 2013-01-14 2015-05-26 International Business Machines Corporation Rewriting relational expressions for different type systems
US9916130B2 (en) 2014-11-03 2018-03-13 Arm Limited Apparatus and method for vector processing
GB2560766B (en) * 2017-03-24 2019-04-03 Imagination Tech Ltd Floating point to fixed point conversion
US20230068781A1 (en) * 2021-08-31 2023-03-02 Intel Corporation Bfloat16 scale and/or reduce instructions
US20230061618A1 (en) * 2021-08-31 2023-03-02 Intel Corporation Bfloat16 square root and/or reciprocal square root instructions
EP4318227A1 (en) * 2022-08-03 2024-02-07 Intel Corporation 8-bit floating point square root and/or reciprocal square root instructions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3551665A (en) * 1966-09-13 1970-12-29 Ibm Floating point binary adder utilizing completely sequential hardware
US4037094A (en) * 1971-08-31 1977-07-19 Texas Instruments Incorporated Multi-functional arithmetic and logical unit
JPS5833572B2 (ja) * 1977-10-21 1983-07-20 株式会社東芝 情報処理方式
JPS5776634A (en) * 1980-10-31 1982-05-13 Hitachi Ltd Digital signal processor
JPS57196355A (en) * 1981-05-27 1982-12-02 Toshiba Corp Data processor
US4417314A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Parallel operating mode arithmetic logic unit apparatus
US4475237A (en) * 1981-11-27 1984-10-02 Tektronix, Inc. Programmable range recognizer for a logic analyzer
US4454589A (en) * 1982-03-12 1984-06-12 The Unite States of America as represented by the Secretary of the Air Force Programmable arithmetic logic unit
JPS59149539A (ja) * 1983-01-28 1984-08-27 Toshiba Corp 固定小数点−浮動小数点変換装置
US4524345A (en) * 1983-02-14 1985-06-18 Prime Computer, Inc. Serial comparison flag detector

Also Published As

Publication number Publication date
GB2186105A (en) 1987-08-05
JPS62197823A (ja) 1987-09-01
DE3701599A1 (de) 1987-08-06
US4815021A (en) 1989-03-21
GB8701631D0 (en) 1987-03-04
GB2186105B (en) 1989-10-25
JPH0544686B2 (US06650917-20031118-M00005.png) 1993-07-07
FR2593620A1 (fr) 1987-07-31

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: STAR TECHNOLOGIES, INC., STERLING, VA., US

8128 New person/name/address of the agent

Representative=s name: REINHARD, H., DIPL.-CHEM. DR.RER.NAT. SKUHRA, U.,

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee