DE3685944T2 - Nichtgesaettigte stromhalbleiteranordnung mit zwei strompfaden. - Google Patents

Nichtgesaettigte stromhalbleiteranordnung mit zwei strompfaden.

Info

Publication number
DE3685944T2
DE3685944T2 DE8686308406T DE3685944T DE3685944T2 DE 3685944 T2 DE3685944 T2 DE 3685944T2 DE 8686308406 T DE8686308406 T DE 8686308406T DE 3685944 T DE3685944 T DE 3685944T DE 3685944 T2 DE3685944 T2 DE 3685944T2
Authority
DE
Germany
Prior art keywords
regions
semiconductor
current
potential
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686308406T
Other languages
German (de)
English (en)
Other versions
DE3685944D1 (de
Inventor
Istvan Barsony
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Publication of DE3685944D1 publication Critical patent/DE3685944D1/de
Application granted granted Critical
Publication of DE3685944T2 publication Critical patent/DE3685944T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/87—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of PN-junction gate FETs

Landscapes

  • Junction Field-Effect Transistors (AREA)
DE8686308406T 1985-11-01 1986-10-29 Nichtgesaettigte stromhalbleiteranordnung mit zwei strompfaden. Expired - Fee Related DE3685944T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60244091A JPS62105478A (ja) 1985-11-01 1985-11-01 半導体装置

Publications (2)

Publication Number Publication Date
DE3685944D1 DE3685944D1 (de) 1992-08-13
DE3685944T2 true DE3685944T2 (de) 1993-03-04

Family

ID=17113607

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686308406T Expired - Fee Related DE3685944T2 (de) 1985-11-01 1986-10-29 Nichtgesaettigte stromhalbleiteranordnung mit zwei strompfaden.

Country Status (4)

Country Link
US (1) US4920400A (enExample)
EP (1) EP0225716B1 (enExample)
JP (1) JPS62105478A (enExample)
DE (1) DE3685944T2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2752991B2 (ja) * 1988-07-14 1998-05-18 株式会社東芝 半導体装置
US5103415A (en) * 1989-01-13 1992-04-07 Kabushiki Kaisha Toshiba Computer-simulation technique for numerical analysis of semiconductor devices
US6201267B1 (en) 1999-03-01 2001-03-13 Rensselaer Polytechnic Institute Compact low power complement FETs

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3840888A (en) * 1969-12-30 1974-10-08 Ibm Complementary mosfet device structure
JPS526076B1 (enExample) * 1971-04-28 1977-02-18
DE2636873A1 (de) * 1976-08-17 1978-02-23 Siemens Ag Halbleiterbauelement mit zwei gekreuzten teildioden und mit transistorartigen eigenschaften
US4284997A (en) * 1977-07-07 1981-08-18 Zaidan Hojin Handotai Kenkyu Shinkokai Static induction transistor and its applied devices

Also Published As

Publication number Publication date
US4920400A (en) 1990-04-24
JPH0354870B2 (enExample) 1991-08-21
JPS62105478A (ja) 1987-05-15
EP0225716A3 (en) 1987-10-28
DE3685944D1 (de) 1992-08-13
EP0225716A2 (en) 1987-06-16
EP0225716B1 (en) 1992-07-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: RESEARCH DEVELOPMENT CORP. OF JAPAN, TOKIO/TOKYO,

8339 Ceased/non-payment of the annual fee