DE3685616D1 - Phasenverriegelte taktregenerierschaltung fuer digitale uebertragungssysteme. - Google Patents

Phasenverriegelte taktregenerierschaltung fuer digitale uebertragungssysteme.

Info

Publication number
DE3685616D1
DE3685616D1 DE8686305243T DE3685616T DE3685616D1 DE 3685616 D1 DE3685616 D1 DE 3685616D1 DE 8686305243 T DE8686305243 T DE 8686305243T DE 3685616 T DE3685616 T DE 3685616T DE 3685616 D1 DE3685616 D1 DE 3685616D1
Authority
DE
Germany
Prior art keywords
phase locked
transmission systems
digital transmission
regeneration circuit
locked clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686305243T
Other languages
English (en)
Other versions
DE3685616T2 (de
Inventor
Yasuharu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26481067&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3685616(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from JP60152026A external-priority patent/JPH0763163B2/ja
Priority claimed from JP60152024A external-priority patent/JPS6212224A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3685616D1 publication Critical patent/DE3685616D1/de
Application granted granted Critical
Publication of DE3685616T2 publication Critical patent/DE3685616T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE8686305243T 1985-07-09 1986-07-07 Phasenverriegelte taktregenerierschaltung fuer digitale uebertragungssysteme. Expired - Lifetime DE3685616T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60152026A JPH0763163B2 (ja) 1985-07-09 1985-07-09 デイジタル伝送方式
JP60152024A JPS6212224A (ja) 1985-07-09 1985-07-09 タイミング抽出回路

Publications (2)

Publication Number Publication Date
DE3685616D1 true DE3685616D1 (de) 1992-07-16
DE3685616T2 DE3685616T2 (de) 1993-02-04

Family

ID=26481067

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686305243T Expired - Lifetime DE3685616T2 (de) 1985-07-09 1986-07-07 Phasenverriegelte taktregenerierschaltung fuer digitale uebertragungssysteme.

Country Status (5)

Country Link
US (1) US4823363A (de)
EP (1) EP0209306B1 (de)
AU (1) AU596803B2 (de)
CA (1) CA1296398C (de)
DE (1) DE3685616T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2550985B2 (ja) * 1987-04-21 1996-11-06 日本電気株式会社 Ｃｍｉ符号復号器
EP0344402B1 (de) * 1988-06-03 1994-08-24 KE KOMMUNIKATIONS-ELEKTRONIK GMBH & CO Verfahren zum Übertragen von Daten über Lichtwellenleiter
US5040190A (en) * 1989-12-22 1991-08-13 Adtran Analog data station terminal
JPH04260239A (ja) * 1991-02-15 1992-09-16 Nec Corp タイミング抽出回路
US5195110A (en) * 1991-04-01 1993-03-16 Nec America, Inc. Clock recovery and decoder circuit for a CMI-encoded signal
GB9117635D0 (en) * 1991-08-15 1991-10-02 British Telecomm Phase shifter
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
DE69226150T2 (de) * 1991-11-05 1999-02-18 Hsu Fu Chieh Redundanzarchitektur für Schaltungsmodul
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US5301196A (en) * 1992-03-16 1994-04-05 International Business Machines Corporation Half-speed clock recovery and demultiplexer circuit
AU4798793A (en) * 1992-08-10 1994-03-03 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5889936A (en) * 1995-11-22 1999-03-30 Cypress Semiconductor Corporation High speed asynchronous digital testing module
SE9701805L (sv) * 1997-05-15 1998-11-16 Ericsson Telefon Ab L M Fasadetektoranordning
US7906982B1 (en) 2006-02-28 2011-03-15 Cypress Semiconductor Corporation Interface apparatus and methods of testing integrated circuits using the same
JP4548527B2 (ja) * 2008-07-31 2010-09-22 ソニー株式会社 情報処理装置、及び信号処理方法
US9759772B2 (en) 2011-10-28 2017-09-12 Teradyne, Inc. Programmable test instrument
US10776233B2 (en) 2011-10-28 2020-09-15 Teradyne, Inc. Programmable test instrument
US10382245B1 (en) * 2018-06-27 2019-08-13 Rohde & Schwarz Gmbh & Co. Kg Method for compressing IQ measurement data
CN109639608B (zh) * 2018-12-18 2020-08-11 深圳市华星光电技术有限公司 数据编码的方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760111A (en) * 1970-06-20 1973-09-18 Nippon Electric Co Pulse regenerative repeater for a multilevel pulse communication system
US3983501A (en) * 1975-09-29 1976-09-28 The United States Of America As Represented By The Secretary Of The Navy Hybrid tracking loop for detecting phase shift keyed signals
JPS5914939B2 (ja) * 1976-09-30 1984-04-06 日本電気株式会社 搬送波再生装置
US4217551A (en) * 1977-07-25 1980-08-12 Intech Laboratories, Inc. Phase modulated data transmission system
JPS5575363A (en) * 1978-12-01 1980-06-06 Nec Corp Timing extracting circuit
US4393516A (en) * 1979-03-09 1983-07-12 Electric Power Research Institute, Inc. Data transmission system and method
JPS6016145B2 (ja) * 1979-03-20 1985-04-24 株式会社日立製作所 クロツク信号抽出方式
US4274067A (en) * 1979-09-27 1981-06-16 Communications Satellite Corporation Universal clock recovery network for QPSK modems
US4380815A (en) * 1981-02-25 1983-04-19 Rockwell International Corporation Simplified NRZ data phase detector with expanded measuring interval
FR2539261B1 (fr) * 1983-01-07 1989-07-13 Telecommunications Sa Emetteur pour faisceaux hertziens numeriques a multi-etats
US4617679A (en) * 1983-09-20 1986-10-14 Nec Electronics U.S.A., Inc. Digital phase lock loop circuit
CA1207845A (en) * 1984-07-23 1986-07-15 Leslie M. Koskinen Adaptively tuned clock recovery circuit
JPH0732391B2 (ja) * 1985-05-28 1995-04-10 日本電気株式会社 クロック同期回路
US4635280A (en) * 1985-05-28 1987-01-06 Harris Corporation Bit synchronizer for decoding data

Also Published As

Publication number Publication date
EP0209306B1 (de) 1992-06-10
EP0209306A2 (de) 1987-01-21
AU5984586A (en) 1987-01-15
EP0209306A3 (en) 1988-11-30
CA1296398C (en) 1992-02-25
AU596803B2 (en) 1990-05-17
DE3685616T2 (de) 1993-02-04
US4823363A (en) 1989-04-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8310 Action for declaration of annulment
8313 Request for invalidation rejected/withdrawn