DE3866685D1 - Entprellschaltung fuer digitale schaltkreise. - Google Patents

Entprellschaltung fuer digitale schaltkreise.

Info

Publication number
DE3866685D1
DE3866685D1 DE8888120115T DE3866685T DE3866685D1 DE 3866685 D1 DE3866685 D1 DE 3866685D1 DE 8888120115 T DE8888120115 T DE 8888120115T DE 3866685 T DE3866685 T DE 3866685T DE 3866685 D1 DE3866685 D1 DE 3866685D1
Authority
DE
Germany
Prior art keywords
digital circuits
delete circuit
delete
circuit
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888120115T
Other languages
English (en)
Inventor
Pierangelo Confalonieri
Sergio Pernici
Germano Nicollini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE3866685D1 publication Critical patent/DE3866685D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
DE8888120115T 1987-12-14 1988-12-02 Entprellschaltung fuer digitale schaltkreise. Expired - Fee Related DE3866685D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8722987A IT1233424B (it) 1987-12-14 1987-12-14 Circuito antirimbalzo per circuiti digitali.

Publications (1)

Publication Number Publication Date
DE3866685D1 true DE3866685D1 (de) 1992-01-16

Family

ID=11202595

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888120115T Expired - Fee Related DE3866685D1 (de) 1987-12-14 1988-12-02 Entprellschaltung fuer digitale schaltkreise.

Country Status (4)

Country Link
US (1) US4883993A (de)
EP (1) EP0320711B1 (de)
DE (1) DE3866685D1 (de)
IT (1) IT1233424B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1243301B (it) * 1990-05-25 1994-05-26 Sgs Thomson Microelectronics Circuito di filtraggio di un segnale logico affetto da spikes di commutazione
US5146111A (en) * 1991-04-10 1992-09-08 International Business Machines Corporation Glitch-proof powered-down on chip receiver with non-overlapping outputs
US5394321A (en) * 1992-09-02 1995-02-28 Electric Power Research Institute, Inc. Quasi square-wave back-EMF permanent magnet AC machines with five or more phases
US5418479A (en) * 1993-12-27 1995-05-23 Intel Corporation Method and circuitry for generating a safe address transition pulse in a memory device
KR100221086B1 (ko) * 1996-01-17 1999-09-15 윤종용 모뎀의 신호 안정화 통화 유지 장치
KR19980051638A (ko) * 1996-12-23 1998-09-25 김광호 신호감시회로
US6134252A (en) * 1997-04-11 2000-10-17 Advanced Micro Devices, Inc. Enhanced glitch removal circuit
DE19733733C2 (de) 1997-08-04 1999-09-02 Siemens Ag Verfahren und Schaltungsanordnung zur Bearbeitung digitaler Signale
US20050238539A1 (en) * 2004-04-01 2005-10-27 Gal Shafirstein Apparatus for automated fresh tissue sectioning

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH533926A (de) * 1971-01-22 1973-02-15 Dixi Sa Entstörschaltung für logische Signale und Verfahren zum Betriebe derselben
US3725792A (en) * 1972-01-07 1973-04-03 Tektronix Inc Jitter-free trigger control circuit
JPS5245859A (en) * 1975-10-08 1977-04-11 Seiko Epson Corp Input circuit
JPS567520A (en) * 1979-07-02 1981-01-26 Mitsubishi Electric Corp Chattering rejection circuit
JPS5685929A (en) * 1979-12-15 1981-07-13 Casio Comput Co Ltd Switch circuit
US4506165A (en) * 1982-06-30 1985-03-19 At&T Bell Laboratories Noise rejection Set-Reset Flip-Flop circuitry

Also Published As

Publication number Publication date
IT8722987A0 (it) 1987-12-14
US4883993A (en) 1989-11-28
EP0320711A3 (en) 1989-09-27
EP0320711A2 (de) 1989-06-21
EP0320711B1 (de) 1991-12-04
IT1233424B (it) 1992-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee