DE3578628D1 - Digitale phasenregelkreisschaltung. - Google Patents

Digitale phasenregelkreisschaltung.

Info

Publication number
DE3578628D1
DE3578628D1 DE8585901812T DE3578628T DE3578628D1 DE 3578628 D1 DE3578628 D1 DE 3578628D1 DE 8585901812 T DE8585901812 T DE 8585901812T DE 3578628 T DE3578628 T DE 3578628T DE 3578628 D1 DE3578628 D1 DE 3578628D1
Authority
DE
Germany
Prior art keywords
control circuit
phase control
digital phase
digital
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585901812T
Other languages
English (en)
Inventor
Hamid Najafi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3578628D1 publication Critical patent/DE3578628D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE8585901812T 1984-04-06 1985-03-19 Digitale phasenregelkreisschaltung. Expired - Lifetime DE3578628D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/597,767 US4628519A (en) 1984-04-06 1984-04-06 Digital phase-locked loop circuit
PCT/US1985/000487 WO1985004775A1 (en) 1984-04-06 1985-03-19 Digital phase-locked loop circuit

Publications (1)

Publication Number Publication Date
DE3578628D1 true DE3578628D1 (de) 1990-08-16

Family

ID=24392846

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585901812T Expired - Lifetime DE3578628D1 (de) 1984-04-06 1985-03-19 Digitale phasenregelkreisschaltung.

Country Status (5)

Country Link
US (1) US4628519A (de)
EP (1) EP0176561B1 (de)
JP (1) JPH0630492B2 (de)
DE (1) DE3578628D1 (de)
WO (1) WO1985004775A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1184024B (it) * 1985-12-17 1987-10-22 Cselt Centro Studi Lab Telecom Perfezionamenti ai circuiti ad aggancio di fase numerici
IT1210836B (it) * 1987-06-26 1989-09-29 Sip Strumento per la misura del rumore di fase di segnali analogici
IT1222405B (it) * 1987-07-30 1990-09-05 Gte Telecom Spa Estrattore digitale di segnale orologio con aggancio e correzione di fase per segnali bipolari
EP0312671B1 (de) * 1987-10-19 1993-01-27 International Business Machines Corporation Prädiktive Taktwiedergewinnungsschaltung
US5121417A (en) * 1988-09-02 1992-06-09 Eastman Kodak Company Count-locked loop timing generator
EP0392264A3 (de) * 1989-04-12 1992-06-24 Siemens Aktiengesellschaft Verfahren zur Gewinnung des Empfangtaktes
JP2824517B2 (ja) * 1989-11-25 1998-11-11 株式会社日立製作所 同期化回路
US6339833B1 (en) * 1998-04-17 2002-01-15 Advanced Micro Devices, Inc. Automatic recovery from clock signal loss

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585298A (en) * 1969-12-30 1971-06-15 Ibm Timing recovery circuit with two speed phase correction
US3864529A (en) * 1972-09-14 1975-02-04 Lynch Communication Systems Receiver for decoding duobinary signals
JPS561823B2 (de) * 1973-12-30 1981-01-16
GB1585080A (en) * 1976-11-06 1981-02-25 Marconi Co Ltd Circuit for producing synchronisation pulses
JPS53101257A (en) * 1977-02-16 1978-09-04 Nippon Telegr & Teleph Corp <Ntt> Synchronous circuit
JPS5546627A (en) * 1978-09-28 1980-04-01 Fujitsu Ltd Timing phase synchronization system
US4339823A (en) * 1980-08-15 1982-07-13 Motorola, Inc. Phase corrected clock signal recovery circuit

Also Published As

Publication number Publication date
EP0176561A4 (de) 1986-07-24
EP0176561A1 (de) 1986-04-09
WO1985004775A1 (en) 1985-10-24
EP0176561B1 (de) 1990-07-11
JPH0630492B2 (ja) 1994-04-20
US4628519A (en) 1986-12-09
JPS61501812A (ja) 1986-08-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee