DE3579851D1 - Unterbrechungssteuerungsschaltung. - Google Patents

Unterbrechungssteuerungsschaltung.

Info

Publication number
DE3579851D1
DE3579851D1 DE8585108147T DE3579851T DE3579851D1 DE 3579851 D1 DE3579851 D1 DE 3579851D1 DE 8585108147 T DE8585108147 T DE 8585108147T DE 3579851 T DE3579851 T DE 3579851T DE 3579851 D1 DE3579851 D1 DE 3579851D1
Authority
DE
Germany
Prior art keywords
control circuit
interrupt control
interrupt
circuit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585108147T
Other languages
English (en)
Inventor
Sjigeru Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3579851D1 publication Critical patent/DE3579851D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE8585108147T 1984-07-05 1985-07-01 Unterbrechungssteuerungsschaltung. Expired - Fee Related DE3579851D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59139618A JPS6118059A (ja) 1984-07-05 1984-07-05 メモリ回路

Publications (1)

Publication Number Publication Date
DE3579851D1 true DE3579851D1 (de) 1990-10-31

Family

ID=15249480

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585108147T Expired - Fee Related DE3579851D1 (de) 1984-07-05 1985-07-01 Unterbrechungssteuerungsschaltung.

Country Status (4)

Country Link
US (1) US4987535A (de)
EP (1) EP0167140B1 (de)
JP (1) JPS6118059A (de)
DE (1) DE3579851D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268632A (ja) * 1988-09-05 1990-03-08 Toshiba Corp 割込み制御装置
US5081702A (en) * 1989-03-09 1992-01-14 Allied-Signal Inc. Method and apparatus for processing more than one high speed signal through a single high speed input terminal of a microcontroller
US5551033A (en) * 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
US5652890A (en) * 1991-05-17 1997-07-29 Vantus Technologies, Inc. Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode
JPH05233318A (ja) * 1992-02-18 1993-09-10 Nec Corp マイクロプロセッサ
US5412782A (en) 1992-07-02 1995-05-02 3Com Corporation Programmed I/O ethernet adapter with early interrupts for accelerating data transfer
US5530874A (en) * 1993-02-02 1996-06-25 3Com Corporation Network adapter with an indication signal mask and an interrupt signal mask
US5692199A (en) * 1993-10-28 1997-11-25 Elonex I.P. Holdings, Ltd. Personal digital assistant module having a host interconnect bus without an interrupt line and which handles interrupts as addresses associated with specific interrupts in memory
US5689713A (en) * 1995-03-31 1997-11-18 Sun Microsystems, Inc. Method and apparatus for interrupt communication in a packet-switched computer system
KR0156173B1 (ko) * 1995-11-21 1998-11-16 문정환 인터럽트 발생회로
JP2002055830A (ja) 2000-05-29 2002-02-20 Seiko Epson Corp 割込信号生成装置及び割込信号の生成方法
JP4680366B2 (ja) * 2000-10-10 2011-05-11 株式会社岡村製作所 商品陳列装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3999165A (en) * 1973-08-27 1976-12-21 Hitachi, Ltd. Interrupt information interface system
US4004283A (en) * 1974-10-30 1977-01-18 Motorola, Inc. Multiple interrupt microprocessor system
US4315314A (en) * 1977-12-30 1982-02-09 Rca Corporation Priority vectored interrupt having means to supply branch address directly
IT1192603B (it) * 1977-12-30 1988-04-20 Rca Corp Apparato di interruzione di un programma,su base prioritaria,dotato di mezzi per l'alimentazione diretta dell'indirizzo di salto
US4200912A (en) * 1978-07-31 1980-04-29 Motorola, Inc. Processor interrupt system
JPS55123736A (en) * 1979-03-16 1980-09-24 Hitachi Ltd Interrupt control system

Also Published As

Publication number Publication date
EP0167140A3 (en) 1986-09-03
EP0167140A2 (de) 1986-01-08
JPH0326866B2 (de) 1991-04-12
US4987535A (en) 1991-01-22
JPS6118059A (ja) 1986-01-25
EP0167140B1 (de) 1990-09-26

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: MOLL, W., DIPL.-PHYS. DR.RER.NAT., 8000 MUENCHEN DELFS, K., DIPL.-ING. MENGDEHL, U., DIPL.-CHEM. DR.RER.NAT. NIEBUHR, H., DIPL.-PHYS. DR.PHIL.HABIL., 2000 HAMBURG GLAWE, U., DIPL.-PHYS. DR.RER.NAT., PAT.-ANWAELTE, 8000 MUENCHEN

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee