DE3580496D1 - Logische schaltung. - Google Patents
Logische schaltung.Info
- Publication number
- DE3580496D1 DE3580496D1 DE8585301311T DE3580496T DE3580496D1 DE 3580496 D1 DE3580496 D1 DE 3580496D1 DE 8585301311 T DE8585301311 T DE 8585301311T DE 3580496 T DE3580496 T DE 3580496T DE 3580496 D1 DE3580496 D1 DE 3580496D1
- Authority
- DE
- Germany
- Prior art keywords
- logical circuit
- logical
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
- H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
- Junction Field-Effect Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59037460A JPS60182759A (ja) | 1984-02-29 | 1984-02-29 | 論理回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3580496D1 true DE3580496D1 (de) | 1990-12-20 |
Family
ID=12498133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585301311T Expired - Fee Related DE3580496D1 (de) | 1984-02-29 | 1985-02-27 | Logische schaltung. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4656611A (de) |
EP (1) | EP0153860B1 (de) |
JP (1) | JPS60182759A (de) |
KR (1) | KR890004454B1 (de) |
CA (1) | CA1246694A (de) |
DE (1) | DE3580496D1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0226678B1 (de) * | 1985-12-24 | 1989-04-26 | Fujitsu Limited | Logische Schaltung |
US6127857A (en) * | 1997-07-02 | 2000-10-03 | Canon Kabushiki Kaisha | Output buffer or voltage hold for analog of multilevel processing |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5080734A (de) * | 1973-11-14 | 1975-07-01 | ||
DE2657561B1 (de) * | 1976-12-18 | 1978-04-13 | Ibm Deutschland | Nachlade-Referenzschaltungsanordnung fuer einen Halbleiterspeicher |
US4355377A (en) * | 1980-06-30 | 1982-10-19 | Inmos Corporation | Asynchronously equillibrated and pre-charged static ram |
-
1984
- 1984-02-29 JP JP59037460A patent/JPS60182759A/ja active Granted
-
1985
- 1985-02-21 KR KR1019850001065A patent/KR890004454B1/ko not_active IP Right Cessation
- 1985-02-22 US US06/705,321 patent/US4656611A/en not_active Expired - Lifetime
- 1985-02-26 CA CA000475169A patent/CA1246694A/en not_active Expired
- 1985-02-27 DE DE8585301311T patent/DE3580496D1/de not_active Expired - Fee Related
- 1985-02-27 EP EP85301311A patent/EP0153860B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4656611A (en) | 1987-04-07 |
JPH0428179B2 (de) | 1992-05-13 |
JPS60182759A (ja) | 1985-09-18 |
CA1246694A (en) | 1988-12-13 |
KR850006789A (ko) | 1985-10-16 |
KR890004454B1 (ko) | 1989-11-04 |
EP0153860B1 (de) | 1990-11-14 |
EP0153860A2 (de) | 1985-09-04 |
EP0153860A3 (en) | 1987-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |