JPS5546627A - Timing phase synchronization system - Google Patents

Timing phase synchronization system

Info

Publication number
JPS5546627A
JPS5546627A JP11967678A JP11967678A JPS5546627A JP S5546627 A JPS5546627 A JP S5546627A JP 11967678 A JP11967678 A JP 11967678A JP 11967678 A JP11967678 A JP 11967678A JP S5546627 A JPS5546627 A JP S5546627A
Authority
JP
Japan
Prior art keywords
circuit
timing signal
zero
cross point
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11967678A
Other languages
Japanese (ja)
Inventor
Kazuo Murano
Tatsuki Hayashi
Shigeyuki Umigami
Fumio Amano
Yasukazu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11967678A priority Critical patent/JPS5546627A/en
Publication of JPS5546627A publication Critical patent/JPS5546627A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To attain high-speed synchronous drawing by estimating a zero-cross point from a sampled value differing in code among the sampling outputs of timing signal components. CONSTITUTION:Reference frequency (fo) is divided by divider circuit 1 and then applied through pulse control circuit 2 to divider circuit 3, whose output is also applied as sampling pulse (fs) to sampling circuit 4. On the other hand, a timing signal component of mean frequency (ft) is passed through circuit 4 and timing signal component extraction circuit 5 extracts a timing signal. Here, zero-cross point estimation circuit 6 estimates a zero-cross point through linear approximation using a sampled value differing in code among outputs of circuit 5. As a result, the number of pulses to be shifted is sent from pulse-number setting circuit 7 to pulse control circuit 2, where output pulsed of divider circuit 1 are extracted. In this way, phase synchronization can be carried out at a high speed.
JP11967678A 1978-09-28 1978-09-28 Timing phase synchronization system Pending JPS5546627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11967678A JPS5546627A (en) 1978-09-28 1978-09-28 Timing phase synchronization system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11967678A JPS5546627A (en) 1978-09-28 1978-09-28 Timing phase synchronization system

Publications (1)

Publication Number Publication Date
JPS5546627A true JPS5546627A (en) 1980-04-01

Family

ID=14767287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11967678A Pending JPS5546627A (en) 1978-09-28 1978-09-28 Timing phase synchronization system

Country Status (1)

Country Link
JP (1) JPS5546627A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630492B2 (en) * 1984-04-06 1994-04-20 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド Digital phase lock loop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630492B2 (en) * 1984-04-06 1994-04-20 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド Digital phase lock loop circuit

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