JPS5472614A - Sampling control phase synchronous circuit - Google Patents

Sampling control phase synchronous circuit

Info

Publication number
JPS5472614A
JPS5472614A JP14051177A JP14051177A JPS5472614A JP S5472614 A JPS5472614 A JP S5472614A JP 14051177 A JP14051177 A JP 14051177A JP 14051177 A JP14051177 A JP 14051177A JP S5472614 A JPS5472614 A JP S5472614A
Authority
JP
Japan
Prior art keywords
output
signal
oscillator
divided
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14051177A
Other languages
Japanese (ja)
Inventor
Osamu Ichiyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14051177A priority Critical patent/JPS5472614A/en
Publication of JPS5472614A publication Critical patent/JPS5472614A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Radio Relay Systems (AREA)

Abstract

PURPOSE: To enable to reduce error synchronization by comparing the phases between the output of a voltage control oscillator and an input signal by means of the 1st phase comparator, executing sample holding by means of the 1/N divided signal of an input signal and adding the sample holded signal to the output of the 2nd phase comparator for the purpose of control of the oscillator.
CONSTITUTION: The phases between the output of voltage control oscillator 11 and an input signal are compared 12, the input signal is divided 21 into 1/N and the output of comparator 12 is sample-holded 13 by the output of divided signal. On the other hand, the output of oscillator 11 is divided 18 into 1/N, the output of divider 21 is compared with the output of divider 18 by means of phase comparator 19; the output is sent to voltage adder 17 through LPF and is added to a signal from circuit 13 and the output of the added signal is supplied as a control signal to oscillator 11. Therefore, error synchronization can be reduced by phase synchronization within leading-in of the input frequency of phase synchronous circuit.
COPYRIGHT: (C)1979,JPO&Japio
JP14051177A 1977-11-21 1977-11-21 Sampling control phase synchronous circuit Pending JPS5472614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14051177A JPS5472614A (en) 1977-11-21 1977-11-21 Sampling control phase synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14051177A JPS5472614A (en) 1977-11-21 1977-11-21 Sampling control phase synchronous circuit

Publications (1)

Publication Number Publication Date
JPS5472614A true JPS5472614A (en) 1979-06-11

Family

ID=15270340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14051177A Pending JPS5472614A (en) 1977-11-21 1977-11-21 Sampling control phase synchronous circuit

Country Status (1)

Country Link
JP (1) JPS5472614A (en)

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