DE3672683D1 - Spannungserhoeherschaltung. - Google Patents

Spannungserhoeherschaltung.

Info

Publication number
DE3672683D1
DE3672683D1 DE8686302714T DE3672683T DE3672683D1 DE 3672683 D1 DE3672683 D1 DE 3672683D1 DE 8686302714 T DE8686302714 T DE 8686302714T DE 3672683 T DE3672683 T DE 3672683T DE 3672683 D1 DE3672683 D1 DE 3672683D1
Authority
DE
Germany
Prior art keywords
voltage raising
raising circuit
circuit
voltage
raising
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686302714T
Other languages
English (en)
Inventor
Masao Nakano
Yoshihiro Takemae
Kimiaki Sato
Nobumi Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3672683D1 publication Critical patent/DE3672683D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)
DE8686302714T 1985-04-13 1986-04-11 Spannungserhoeherschaltung. Expired - Fee Related DE3672683D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60077547A JP2548908B2 (ja) 1985-04-13 1985-04-13 昇圧回路

Publications (1)

Publication Number Publication Date
DE3672683D1 true DE3672683D1 (de) 1990-08-23

Family

ID=13637035

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686302714T Expired - Fee Related DE3672683D1 (de) 1985-04-13 1986-04-11 Spannungserhoeherschaltung.

Country Status (5)

Country Link
US (1) US4704706A (de)
EP (1) EP0202025B1 (de)
JP (1) JP2548908B2 (de)
KR (1) KR900001818B1 (de)
DE (1) DE3672683D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239399A (ja) * 1986-04-09 1987-10-20 Nec Corp 信号発生装置
JPS63257325A (ja) * 1987-04-14 1988-10-25 Mitsubishi Electric Corp 昇圧信号発生回路
JPS6437797A (en) * 1987-08-03 1989-02-08 Oki Electric Ind Co Ltd Eprom device
JP2607733B2 (ja) * 1990-05-31 1997-05-07 シャープ株式会社 半導体記憶装置の昇圧回路
US5075571A (en) * 1991-01-02 1991-12-24 International Business Machines Corp. PMOS wordline boost cricuit for DRAM
KR940004516B1 (ko) * 1991-08-14 1994-05-25 삼성전자 주식회사 반도체 메모리의 고속 센싱장치
US5255224A (en) * 1991-12-18 1993-10-19 International Business Machines Corporation Boosted drive system for master/local word line memory architecture
JPH0684354A (ja) * 1992-05-26 1994-03-25 Nec Corp 行デコーダ回路
JP2806717B2 (ja) * 1992-10-28 1998-09-30 日本電気アイシーマイコンシステム株式会社 チャージポンプ回路
KR0157334B1 (ko) * 1993-11-17 1998-10-15 김광호 반도체 메모리 장치의 전압 승압회로
GB9423035D0 (en) * 1994-11-15 1995-01-04 Sgs Thomson Microelectronics Voltage boost circuit for a memory device
US5946204A (en) * 1997-12-15 1999-08-31 Pericom Semiconductor Corp. Voltage booster with reduced Vpp current and self-timed control loop without pulse generator
US5847946A (en) * 1997-12-15 1998-12-08 Pericom Semiconductor Corp. Voltage booster with pulsed initial charging and delayed capacitive boost using charge-pumped delay line
JP3726041B2 (ja) * 2001-07-24 2005-12-14 エルピーダメモリ株式会社 昇圧回路およびその駆動方法
JP4808995B2 (ja) * 2005-05-24 2011-11-02 ルネサスエレクトロニクス株式会社 半導体回路装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976892A (en) * 1974-07-01 1976-08-24 Motorola, Inc. Pre-conditioning circuits for MOS integrated circuits
JPS5693422A (en) * 1979-12-05 1981-07-29 Fujitsu Ltd Level-up circuit
JPS57101425A (en) * 1980-12-17 1982-06-24 Fujitsu Ltd Driver circuit
JPS57106228A (en) * 1980-12-24 1982-07-02 Fujitsu Ltd Semiconductor circuit
JPS595488A (ja) * 1982-07-01 1984-01-12 Fujitsu Ltd 半導体装置
US4521701A (en) * 1982-09-16 1985-06-04 Texas Instruments Incorporated High-speed low-power delayed clock generator

Also Published As

Publication number Publication date
EP0202025A3 (en) 1988-08-03
EP0202025B1 (de) 1990-07-18
JP2548908B2 (ja) 1996-10-30
KR900001818B1 (en) 1990-03-24
KR860008561A (ko) 1986-11-17
JPS61239721A (ja) 1986-10-25
US4704706A (en) 1987-11-03
EP0202025A2 (de) 1986-11-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee