DE3585402D1 - Dynamischer ram, und verfahren zur stabilisierung der stromstoesse in solch einer speicherschaltung. - Google Patents

Dynamischer ram, und verfahren zur stabilisierung der stromstoesse in solch einer speicherschaltung.

Info

Publication number
DE3585402D1
DE3585402D1 DE8585305818T DE3585402T DE3585402D1 DE 3585402 D1 DE3585402 D1 DE 3585402D1 DE 8585305818 T DE8585305818 T DE 8585305818T DE 3585402 T DE3585402 T DE 3585402T DE 3585402 D1 DE3585402 D1 DE 3585402D1
Authority
DE
Germany
Prior art keywords
stabilizing
electricity
memory circuit
dynamic ram
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585305818T
Other languages
English (en)
Inventor
James D Allan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thorn EMI North America Inc
Original Assignee
Thorn EMI North America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thorn EMI North America Inc filed Critical Thorn EMI North America Inc
Application granted granted Critical
Publication of DE3585402D1 publication Critical patent/DE3585402D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE8585305818T 1984-11-19 1985-08-15 Dynamischer ram, und verfahren zur stabilisierung der stromstoesse in solch einer speicherschaltung. Expired - Lifetime DE3585402D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/672,907 US4656612A (en) 1984-11-19 1984-11-19 Dram current control technique

Publications (1)

Publication Number Publication Date
DE3585402D1 true DE3585402D1 (de) 1992-03-26

Family

ID=24700524

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585305818T Expired - Lifetime DE3585402D1 (de) 1984-11-19 1985-08-15 Dynamischer ram, und verfahren zur stabilisierung der stromstoesse in solch einer speicherschaltung.

Country Status (5)

Country Link
US (1) US4656612A (de)
EP (1) EP0182457B1 (de)
JP (1) JPH07111827B2 (de)
KR (1) KR910002801B1 (de)
DE (1) DE3585402D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825416A (en) * 1986-05-07 1989-04-25 Advanced Micro Devices, Inc. Integrated electronic memory circuit with internal timing and operable in both latch-based and register-based systems
JPH0812760B2 (ja) * 1986-11-29 1996-02-07 三菱電機株式会社 ダイナミックメモリ装置
JPH06101227B2 (ja) * 1986-11-29 1994-12-12 三菱電機株式会社 半導体メモリ装置
US4979190A (en) * 1988-04-01 1990-12-18 Digital Equipment Corporation Method and apparatus for stabilized data transmission
JPH01263995A (ja) * 1988-04-13 1989-10-20 Nec Corp ダイナミック型半導体記憶素子
JP2534757B2 (ja) * 1988-07-06 1996-09-18 株式会社東芝 リフレッシュ回路
KR910002033B1 (ko) * 1988-07-11 1991-03-30 삼성전자 주식회사 메모리 셀의 센스앰프 구동회로
US5031150A (en) * 1988-08-26 1991-07-09 Kabushiki Kaisha Toshiba Control circuit for a semiconductor memory device and semiconductor memory system
US4985865A (en) * 1988-12-21 1991-01-15 Texas Instruments Incorporated Asymmetrical delay for controlling word line selection
JP2614514B2 (ja) * 1989-05-19 1997-05-28 三菱電機株式会社 ダイナミック・ランダム・アクセス・メモリ
JP2925600B2 (ja) * 1989-11-07 1999-07-28 富士通株式会社 半導体記憶装置
US5163168A (en) * 1990-03-30 1992-11-10 Matsushita Electric Industrial Co., Ltd. Pulse signal generator and redundancy selection signal generator
EP0467638B1 (de) * 1990-07-17 1997-05-07 Nec Corporation Halbleiterspeicheranordnung
US5313422A (en) * 1991-05-29 1994-05-17 Texas Instruments Incorporated Digitally controlled delay applied to address decoder for write vs. read
US5359630A (en) * 1992-08-13 1994-10-25 Digital Equipment Corporation Method and apparatus for realignment of synchronous data
US6463396B1 (en) * 1994-05-31 2002-10-08 Kabushiki Kaisha Toshiba Apparatus for controlling internal heat generating circuit
US5532969A (en) * 1994-10-07 1996-07-02 International Business Machines Corporation Clocking circuit with increasing delay as supply voltage VDD
US5602785A (en) * 1995-12-13 1997-02-11 Micron Technology, Inc. P-channel sense amplifier pull-up circuit with a timed pulse for use in DRAM memories having non-bootstrapped word lines
US6535798B1 (en) * 1998-12-03 2003-03-18 Intel Corporation Thermal management in a system
KR100300079B1 (ko) 1999-07-28 2001-11-01 김영환 센스앰프 구동회로

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3705392A (en) * 1971-09-07 1972-12-05 Texas Instruments Inc Mos dynamic memory
US3996481A (en) * 1974-11-19 1976-12-07 International Business Machines Corporation FET load gate compensator
US4081701A (en) * 1976-06-01 1978-03-28 Texas Instruments Incorporated High speed sense amplifier for MOS random access memory
JPS5441633A (en) * 1977-09-09 1979-04-03 Hitachi Ltd Readout system for memory cell
JPS594790B2 (ja) * 1978-05-18 1984-01-31 株式会社東芝 メモリ−回路
JPS54150064A (en) * 1978-05-18 1979-11-24 Toshiba Corp Pulse generation circuit
US4222112A (en) * 1979-02-09 1980-09-09 Bell Telephone Laboratories, Incorporated Dynamic RAM organization for reducing peak current
DE3101520A1 (de) * 1981-01-19 1982-08-26 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter halbleiterspeicher
US4421996A (en) * 1981-10-09 1983-12-20 Advanced Micro Devices, Inc. Sense amplification scheme for random access memory
JPS6053400B2 (ja) * 1981-12-04 1985-11-25 富士通株式会社 スタテイツク型メモリ回路
JPS5987696A (ja) * 1982-11-10 1984-05-21 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド センス率の制御装置
JPS5998390A (ja) * 1982-11-26 1984-06-06 Hitachi Ltd ダイナミツク型ｍｏｓｒａｍ
US4551641A (en) * 1983-11-23 1985-11-05 Motorola, Inc. Sense amplifier

Also Published As

Publication number Publication date
EP0182457A3 (en) 1989-05-10
JPH07111827B2 (ja) 1995-11-29
KR910002801B1 (ko) 1991-05-04
EP0182457B1 (de) 1992-02-19
EP0182457A2 (de) 1986-05-28
JPS61126693A (ja) 1986-06-14
US4656612A (en) 1987-04-07
KR860004348A (ko) 1986-06-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee