JPS5441633A - Readout system for memory cell - Google Patents

Readout system for memory cell

Info

Publication number
JPS5441633A
JPS5441633A JP10778877A JP10778877A JPS5441633A JP S5441633 A JPS5441633 A JP S5441633A JP 10778877 A JP10778877 A JP 10778877A JP 10778877 A JP10778877 A JP 10778877A JP S5441633 A JPS5441633 A JP S5441633A
Authority
JP
Japan
Prior art keywords
memory cell
readout system
cell
dummy cell
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10778877A
Other languages
Japanese (ja)
Inventor
Akira Endo
Yoshiaki Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10778877A priority Critical patent/JPS5441633A/en
Publication of JPS5441633A publication Critical patent/JPS5441633A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators

Abstract

PURPOSE:To prevent misread-out and to speed up the access time, by leading the readout signal for dummy cell delayed by the memory cell, in the memory cell and the dummy cell connected to the presense amplifier.
JP10778877A 1977-09-09 1977-09-09 Readout system for memory cell Pending JPS5441633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10778877A JPS5441633A (en) 1977-09-09 1977-09-09 Readout system for memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10778877A JPS5441633A (en) 1977-09-09 1977-09-09 Readout system for memory cell

Publications (1)

Publication Number Publication Date
JPS5441633A true JPS5441633A (en) 1979-04-03

Family

ID=14468033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10778877A Pending JPS5441633A (en) 1977-09-09 1977-09-09 Readout system for memory cell

Country Status (1)

Country Link
JP (1) JPS5441633A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61126693A (en) * 1984-11-19 1986-06-14 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Stabilization of current during sensing action and return action of dynamic random access memory circuit, circuit itself and compensation for temperature changes and power source variations of circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61126693A (en) * 1984-11-19 1986-06-14 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Stabilization of current during sensing action and return action of dynamic random access memory circuit, circuit itself and compensation for temperature changes and power source variations of circuit

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