DE3583704D1 - Doppelrang-abtasthalteschaltung und verfahren. - Google Patents

Doppelrang-abtasthalteschaltung und verfahren.

Info

Publication number
DE3583704D1
DE3583704D1 DE8585107271T DE3583704T DE3583704D1 DE 3583704 D1 DE3583704 D1 DE 3583704D1 DE 8585107271 T DE8585107271 T DE 8585107271T DE 3583704 T DE3583704 T DE 3583704T DE 3583704 D1 DE3583704 D1 DE 3583704D1
Authority
DE
Germany
Prior art keywords
sensor circuit
double rank
rank sensor
double
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585107271T
Other languages
English (en)
Inventor
Bruce J Penney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Application granted granted Critical
Publication of DE3583704D1 publication Critical patent/DE3583704D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE8585107271T 1984-06-13 1985-06-12 Doppelrang-abtasthalteschaltung und verfahren. Expired - Fee Related DE3583704D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/620,233 US4584559A (en) 1984-06-13 1984-06-13 Dual rank sample and hold circuit and method

Publications (1)

Publication Number Publication Date
DE3583704D1 true DE3583704D1 (de) 1991-09-12

Family

ID=24485113

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585107271T Expired - Fee Related DE3583704D1 (de) 1984-06-13 1985-06-12 Doppelrang-abtasthalteschaltung und verfahren.

Country Status (4)

Country Link
US (1) US4584559A (de)
EP (1) EP0165553B1 (de)
JP (1) JPS618800A (de)
DE (1) DE3583704D1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4712061A (en) * 1986-02-24 1987-12-08 Gould Inc. Small propagation delay measurement for digital logic
US4823128A (en) * 1986-05-19 1989-04-18 Tektronix, Inc. Digital-to-analog converter filter for producing a continuous analog signal output without distortion
US4760319A (en) * 1987-02-27 1988-07-26 Magnetic Peripherals Inc. Circuit for removing unwanted slope transitions from an incoming signal
US4968989A (en) * 1987-04-20 1990-11-06 Olmstead John A Switched capacitor filter for use with a digital-to-analog (D/A) converter
US4873457A (en) * 1988-07-05 1989-10-10 Tektronix, Inc. Integrated sample and hold circuit
US4885545A (en) * 1988-08-08 1989-12-05 Tektronix, Inc. High speed circuit with supporting auxiliary circuit
JPH039874A (ja) * 1989-06-06 1991-01-17 Nec Software Ltd 認承印押下自動化システム
US5162670A (en) * 1990-01-26 1992-11-10 Kabushiki Kaisha Toshiba Sample-and-hold circuit device
JPH0736523B2 (ja) * 1990-08-14 1995-04-19 菊水電子工業株式会社 直線補間器
US5111072A (en) * 1990-08-29 1992-05-05 Ncr Corporation Sample-and-hold switch with low on resistance and reduced charge injection
US5134403A (en) * 1990-12-06 1992-07-28 Hewlett-Packard Co. High speed sampling and digitizing system requiring no hold circuit
US5646620A (en) * 1995-06-02 1997-07-08 National Instruments Corporation Method and apparatus for deglitching DAC signals
US5614903A (en) * 1995-08-29 1997-03-25 Trw Inc. Distortion suppressor for digital-to-analog converter
US6304199B1 (en) * 1999-05-05 2001-10-16 Maxim Integrated Products, Inc. Method and apparatus for deglitching digital to analog converters
US6362666B1 (en) * 1999-12-30 2002-03-26 Intel Corporation Precision and fast recovery buffer
US6417793B1 (en) * 2000-02-04 2002-07-09 Rockwell Technologies, Llc Track/attenuate circuit and method for switched current source DAC
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7002506B1 (en) * 2004-12-23 2006-02-21 Texas Instruments Incorporated Providing pipe line ADC with acceptable bit error and power efficiency combination
US7734866B2 (en) * 2005-08-04 2010-06-08 Rambus Inc. Memory with address-differentiated refresh rate to accommodate low-retention storage rows
US7724042B2 (en) * 2007-07-06 2010-05-25 Texas Instruments Incorporated Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity
EP2723573B1 (de) * 2011-06-27 2021-04-28 Hewlett-Packard Development Company, L.P. Tintenpegelsensor und zugehörige verfahren
US9692442B1 (en) 2016-09-30 2017-06-27 Cypress Semiconductor Corporation Digital-to-analog converter with a sample and hold circuit and a continuous-time programmable block
US10348250B2 (en) * 2017-10-23 2019-07-09 Analog Devices Global Unlimited Company Amplifier with noise control and a digital to analog converter with reduced noise bandwidth

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4348768A (en) * 1977-09-06 1982-09-07 International Telephone And Telegraph Corporation PCM Codec using common D/A converter for encoding and decoding
US4302689A (en) * 1979-08-02 1981-11-24 John Fluke Mfg. Co., Inc. Sample and hold circuit

Also Published As

Publication number Publication date
EP0165553A2 (de) 1985-12-27
EP0165553B1 (de) 1991-08-07
US4584559A (en) 1986-04-22
JPS618800A (ja) 1986-01-16
JPH0313677B2 (de) 1991-02-25
EP0165553A3 (en) 1988-01-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee