DE3582990D1 - Logikschaltung mit dynamisch steuerbarem ausgang. - Google Patents
Logikschaltung mit dynamisch steuerbarem ausgang.Info
- Publication number
- DE3582990D1 DE3582990D1 DE8585306858T DE3582990T DE3582990D1 DE 3582990 D1 DE3582990 D1 DE 3582990D1 DE 8585306858 T DE8585306858 T DE 8585306858T DE 3582990 T DE3582990 T DE 3582990T DE 3582990 D1 DE3582990 D1 DE 3582990D1
- Authority
- DE
- Germany
- Prior art keywords
- signal
- feedback
- clock
- logic
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
- Microcomputers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US65610984A | 1984-09-28 | 1984-09-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3582990D1 true DE3582990D1 (de) | 1991-07-04 |
Family
ID=24631665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585306858T Expired - Lifetime DE3582990D1 (de) | 1984-09-28 | 1985-09-26 | Logikschaltung mit dynamisch steuerbarem ausgang. |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0177280B1 (de) |
JP (1) | JPS6186855A (de) |
AT (1) | ATE64044T1 (de) |
DE (1) | DE3582990D1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4758747A (en) * | 1986-05-30 | 1988-07-19 | Advanced Micro Devices, Inc. | Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor |
US4789951A (en) * | 1986-05-16 | 1988-12-06 | Advanced Micro Devices, Inc. | Programmable array logic cell |
US4779229A (en) * | 1986-07-02 | 1988-10-18 | Advanced Micro Devices, Inc. | Prom with programmable output structures |
US4783606A (en) * | 1987-04-14 | 1988-11-08 | Erich Goetting | Programming circuit for programmable logic array I/O cell |
EP0310377B1 (de) * | 1987-10-02 | 1992-06-10 | Kawasaki Steel Corporation | Programmierbare Eingangs-/Ausgangsschaltung |
US4871930A (en) * | 1988-05-05 | 1989-10-03 | Altera Corporation | Programmable logic device with array blocks connected via programmable interconnect |
US4894563A (en) * | 1988-10-11 | 1990-01-16 | Atmel Corporation | Output macrocell for programmable logic device |
JP2566005B2 (ja) * | 1989-03-03 | 1996-12-25 | 株式会社東芝 | 入力切換装置 |
FR2846765B1 (fr) * | 2002-11-04 | 2005-01-14 | St Microelectronics Sa | Registre tampon de sortie, circuit electronique et procede de delivrance de signaux l'utilisant |
JP4790540B2 (ja) * | 2006-08-18 | 2011-10-12 | 富士通セミコンダクター株式会社 | 半導体装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6022774B2 (ja) * | 1977-07-28 | 1985-06-04 | 日本電気株式会社 | 入出力端子制御方式 |
-
1985
- 1985-09-26 JP JP60214438A patent/JPS6186855A/ja active Granted
- 1985-09-26 EP EP85306858A patent/EP0177280B1/de not_active Expired - Lifetime
- 1985-09-26 AT AT85306858T patent/ATE64044T1/de not_active IP Right Cessation
- 1985-09-26 DE DE8585306858T patent/DE3582990D1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0177280A3 (en) | 1988-01-07 |
EP0177280B1 (de) | 1991-05-29 |
ATE64044T1 (de) | 1991-06-15 |
EP0177280A2 (de) | 1986-04-09 |
JPH0568729B2 (de) | 1993-09-29 |
JPS6186855A (ja) | 1986-05-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL |
|
8339 | Ceased/non-payment of the annual fee |