DE3571723D1 - A process for forming vias on integrated circuits - Google Patents

A process for forming vias on integrated circuits

Info

Publication number
DE3571723D1
DE3571723D1 DE8585401638T DE3571723T DE3571723D1 DE 3571723 D1 DE3571723 D1 DE 3571723D1 DE 8585401638 T DE8585401638 T DE 8585401638T DE 3571723 T DE3571723 T DE 3571723T DE 3571723 D1 DE3571723 D1 DE 3571723D1
Authority
DE
Germany
Prior art keywords
integrated circuits
forming vias
vias
forming
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585401638T
Other languages
English (en)
Inventor
Michael E Thomas
Robert L Brown
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Application granted granted Critical
Publication of DE3571723D1 publication Critical patent/DE3571723D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8585401638T 1984-08-23 1985-08-13 A process for forming vias on integrated circuits Expired DE3571723D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US64402884A 1984-08-23 1984-08-23

Publications (1)

Publication Number Publication Date
DE3571723D1 true DE3571723D1 (en) 1989-08-24

Family

ID=24583148

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585401638T Expired DE3571723D1 (en) 1984-08-23 1985-08-13 A process for forming vias on integrated circuits

Country Status (4)

Country Link
EP (1) EP0175604B1 (de)
JP (1) JPS61112356A (de)
CA (1) CA1226680A (de)
DE (1) DE3571723D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
JPS61258453A (ja) * 1985-05-13 1986-11-15 Toshiba Corp 半導体装置の製造方法
GB8518231D0 (en) * 1985-07-19 1985-08-29 Plessey Co Plc Producing layered structures
US4767724A (en) * 1986-03-27 1988-08-30 General Electric Company Unframed via interconnection with dielectric etch stop
IL81849A0 (en) * 1987-03-10 1987-10-20 Zvi Orbach Integrated circuits and a method for manufacture thereof
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits
US4776087A (en) * 1987-04-27 1988-10-11 International Business Machines Corporation VLSI coaxial wiring structure
JP2557898B2 (ja) * 1987-07-31 1996-11-27 株式会社東芝 半導体装置
DE3742669A1 (de) * 1987-12-16 1989-06-29 Siemens Ag Integrierte schaltung und verfahren zur herstellung
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
EP0326956A3 (de) * 1988-02-02 1991-03-13 National Semiconductor Corporation Verfahren um Elemente auf einem Integrierschaltungssubstrat an eine Metalisierungsschicht zu kontaktieren.
EP0373258B1 (de) * 1988-12-16 1993-03-10 Siemens Aktiengesellschaft Verfahren zur selbstjustierten Herstellung von Kontakten zwischen in übereinander angeordneten Verdrahtungsebenen einer integrierten Schaltung enthaltenen Leiterbahnen
US5439848A (en) * 1992-12-30 1995-08-08 Sharp Microelectronics Technology, Inc. Method for fabricating a self-aligned multi-level interconnect
US5834845A (en) * 1995-09-21 1998-11-10 Advanced Micro Devices, Inc. Interconnect scheme for integrated circuits
KR0185298B1 (ko) * 1995-12-30 1999-04-15 김주용 반도체 소자의 콘택홀 매립용 플러그 형성방법
CN105575887B (zh) * 2014-10-16 2018-10-16 中芯国际集成电路制造(上海)有限公司 互连结构的形成方法
CN116169118A (zh) * 2019-12-06 2023-05-26 中国科学院微电子研究所 金属化叠层及其制造方法及包括金属化叠层的电子设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5282083A (en) * 1975-12-27 1977-07-08 Fujitsu Ltd Production of semiconductor device
JPS52132781A (en) * 1976-04-30 1977-11-07 Sony Corp Manufacture for semiconductor device
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
JPS56130951A (en) * 1980-03-17 1981-10-14 Fujitsu Ltd Manufacture of semiconductor device
JPS5856438A (ja) * 1981-09-30 1983-04-04 Fujitsu Ltd 半導体装置の製造方法
JPS58184741A (ja) * 1982-04-23 1983-10-28 Toshiba Corp 半導体装置の製造方法
JPS59550A (ja) * 1982-06-25 1984-01-05 Keiichi Omori 双円形シリンダ−エンジン
JPS5966149A (ja) * 1982-10-08 1984-04-14 Toshiba Corp 半導体装置の製造方法
JPS5967649A (ja) * 1982-10-12 1984-04-17 Hitachi Ltd 多層配線の製造方法
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure

Also Published As

Publication number Publication date
JPS61112356A (ja) 1986-05-30
EP0175604A3 (en) 1986-09-17
EP0175604B1 (de) 1989-07-19
EP0175604A2 (de) 1986-03-26
CA1226680A (en) 1987-09-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee