DE3484053D1 - Uebertragungsverfahren. - Google Patents

Uebertragungsverfahren.

Info

Publication number
DE3484053D1
DE3484053D1 DE8484307877T DE3484053T DE3484053D1 DE 3484053 D1 DE3484053 D1 DE 3484053D1 DE 8484307877 T DE8484307877 T DE 8484307877T DE 3484053 T DE3484053 T DE 3484053T DE 3484053 D1 DE3484053 D1 DE 3484053D1
Authority
DE
Germany
Prior art keywords
protocol
data
communications method
control characters
communicating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484307877T
Other languages
English (en)
Inventor
William Robert Goodman
Frederick Zardiackas
Ted Tawshunsky
Richard Barry Mayfield
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Application granted granted Critical
Publication of DE3484053D1 publication Critical patent/DE3484053D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/1607—Details of the supervisory signal
    • H04L1/1664—Details of the supervisory signal the supervisory signal being transmitted together with payload signals; piggybacking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H04L1/188—Time-out mechanisms
    • H04L1/1883—Time-out mechanisms using multiple timers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H04L1/1887—Scheduling and prioritising arrangements
DE8484307877T 1983-11-14 1984-11-14 Uebertragungsverfahren. Expired - Fee Related DE3484053D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/551,297 US4646300A (en) 1983-11-14 1983-11-14 Communications method

Publications (1)

Publication Number Publication Date
DE3484053D1 true DE3484053D1 (de) 1991-03-07

Family

ID=24200689

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484307877T Expired - Fee Related DE3484053D1 (de) 1983-11-14 1984-11-14 Uebertragungsverfahren.

Country Status (7)

Country Link
US (1) US4646300A (de)
EP (1) EP0145318B1 (de)
JP (1) JPS60117944A (de)
AT (1) ATE60678T1 (de)
AU (1) AU573282B2 (de)
CA (1) CA1226371A (de)
DE (1) DE3484053D1 (de)

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US8686549B2 (en) * 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
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US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
JP2004533691A (ja) * 2001-06-20 2004-11-04 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト データを処理するための方法
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8686475B2 (en) * 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7301961B1 (en) 2001-12-27 2007-11-27 Cypress Semiconductor Corportion Method and apparatus for configuring signal lines according to idle codes
US7073018B1 (en) * 2001-12-27 2006-07-04 Cypress Semiconductor Corporation Device identification method for systems having multiple device branches
WO2003071418A2 (de) * 2002-01-18 2003-08-28 Pact Xpp Technologies Ag Übersetzungsverfahren
WO2003060747A2 (de) * 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
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US8914590B2 (en) * 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
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Also Published As

Publication number Publication date
JPS60117944A (ja) 1985-06-25
AU573282B2 (en) 1988-06-02
US4646300A (en) 1987-02-24
EP0145318B1 (de) 1991-01-30
CA1226371A (en) 1987-09-01
ATE60678T1 (de) 1991-02-15
AU3543984A (en) 1985-05-23
JPH053941B2 (de) 1993-01-18
EP0145318A3 (en) 1987-01-21
EP0145318A2 (de) 1985-06-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee