DE3481254D1 - Lsi-vorrichtung fuer eine toranordnung. - Google Patents

Lsi-vorrichtung fuer eine toranordnung.

Info

Publication number
DE3481254D1
DE3481254D1 DE8484302183T DE3481254T DE3481254D1 DE 3481254 D1 DE3481254 D1 DE 3481254D1 DE 8484302183 T DE8484302183 T DE 8484302183T DE 3481254 T DE3481254 T DE 3481254T DE 3481254 D1 DE3481254 D1 DE 3481254D1
Authority
DE
Germany
Prior art keywords
gate arrangement
lsi device
lsi
gate
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484302183T
Other languages
English (en)
Inventor
Yoshiki Shimauchi
Katsuji Hirochi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3481254D1 publication Critical patent/DE3481254D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/088—Transistor-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
DE8484302183T 1983-03-31 1984-03-30 Lsi-vorrichtung fuer eine toranordnung. Expired - Fee Related DE3481254D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58053613A JPS59181724A (ja) 1983-03-31 1983-03-31 ゲ−トアレイｌｓｉ装置

Publications (1)

Publication Number Publication Date
DE3481254D1 true DE3481254D1 (de) 1990-03-08

Family

ID=12947748

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484302183T Expired - Fee Related DE3481254D1 (de) 1983-03-31 1984-03-30 Lsi-vorrichtung fuer eine toranordnung.

Country Status (4)

Country Link
US (1) US4689502A (de)
EP (1) EP0121424B1 (de)
JP (1) JPS59181724A (de)
DE (1) DE3481254D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2180382B (en) * 1985-09-11 1989-11-22 Pilkington Micro Electronics Semi-conductor integrated circuits/systems
US4939391A (en) * 1986-05-30 1990-07-03 Advanced Micro Devices, Inc. Programmable logic device with observability and preload circuitry for buried state registers
US4870598A (en) * 1987-08-04 1989-09-26 Texas Instruments Incorporated Comprehensive logic circuit layout system
US5150309A (en) * 1987-08-04 1992-09-22 Texas Instruments Incorporated Comprehensive logic circuit layout system
JPH01279633A (ja) * 1988-05-02 1989-11-09 Nec Corp Ｅｃｌ−ｔｔｌレベル変換回路
US5625567A (en) * 1993-11-12 1997-04-29 Viewlogic Systems, Inc. Electronic circuit design system and method with programmable addition and manipulation of logic elements surrounding terminals

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3416043A (en) * 1965-04-12 1968-12-10 Burroughs Corp Integrated anti-ringing clamped logic circuits
US3482111A (en) * 1966-03-04 1969-12-02 Ncr Co High speed logical circuit
US3643232A (en) * 1967-06-05 1972-02-15 Texas Instruments Inc Large-scale integration of electronic systems in microminiature form
US3999080A (en) * 1974-12-23 1976-12-21 Texas Instruments Inc. Transistor coupled logic circuit
US4045689A (en) * 1976-06-01 1977-08-30 National Semiconductor Corporation Circuit for squaring the transfer characteristics of a ttl gate
US4174541A (en) * 1976-12-01 1979-11-13 Raytheon Company Bipolar monolithic integrated circuit memory with standby power enable
US4131808A (en) * 1977-08-04 1978-12-26 Fairchild Camera And Instrument Corporation TTL to MOS driver circuit
US4239981A (en) * 1978-09-25 1980-12-16 Ampex Corporation Fast semiconductor digital logic inverter gate
JPS5830233A (ja) * 1981-08-17 1983-02-22 Fujitsu Ltd トランジスタ回路
JPS5830235A (ja) * 1981-08-18 1983-02-22 Fujitsu Ltd ゲ−トアレイ

Also Published As

Publication number Publication date
JPS59181724A (ja) 1984-10-16
EP0121424A2 (de) 1984-10-10
EP0121424B1 (de) 1990-01-31
US4689502A (en) 1987-08-25
EP0121424A3 (en) 1987-02-04

Similar Documents

Publication Publication Date Title
DE3850855D1 (de) Halbleitervorrichtung.
DE3484827D1 (de) Elektrooptischeeinrichtung.
DE3580953D1 (de) Entladungsvorrichtung.
DE3484514D1 (de) Halbleiterspeichergeraet.
DE3584799D1 (de) Halbleitervorrichtung.
NO157194C (no) Drivinnretning for underkalibret prosjektil.
DE3484232D1 (de) Halbleiterspeichervorrichtung.
DE68921368D1 (de) Gate-Abschalthalbleitereinrichtung.
DE3581370D1 (de) Halbleitervorrichtung.
DE3879850T2 (de) Eingangsschutzvorrichtung fuer eine halbleitervorrichtung.
NL193522B (nl) Vastsnoerinrichting.
IT8421030A0 (it) Dispositivo assortitore.
DE3889354T2 (de) Halbleiteranordnung.
IT8322373A0 (it) Dispositivo semiconduttore.
DE3586568D1 (de) Halbleitereinrichtung.
IT8219677A0 (it) Dispositivo a semiconduttori.
DE3481254D1 (de) Lsi-vorrichtung fuer eine toranordnung.
NL187416C (nl) Stralingsgevoelige halfgeleiderinrichting.
IT1212093B (it) Dispositivo di tensionamento.
BR8406578A (pt) Catraca
IT8324175A0 (it) Dispositivo semiconduttore.
IT8423942A0 (it) Dispositivo semiconduttore.
ES519470A0 (es) Un dispositivo semiconductor.
DE68914885D1 (de) Halbleitervorrichtung.
NO842462L (no) Utsettingsinnretning for baater.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee