DE3423181A1 - Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten - Google Patents

Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten

Info

Publication number
DE3423181A1
DE3423181A1 DE19843423181 DE3423181A DE3423181A1 DE 3423181 A1 DE3423181 A1 DE 3423181A1 DE 19843423181 DE19843423181 DE 19843423181 DE 3423181 A DE3423181 A DE 3423181A DE 3423181 A1 DE3423181 A1 DE 3423181A1
Authority
DE
Germany
Prior art keywords
connecting elements
thin laminates
prepregs
laminates
prelaminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19843423181
Other languages
German (de)
English (en)
Inventor
Rainer 5216 Niederkassel Burger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
President Engineering Corp
Original Assignee
Dielektra 5000 Koeln GmbH
Dielektra GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dielektra 5000 Koeln GmbH, Dielektra GmbH filed Critical Dielektra 5000 Koeln GmbH
Priority to DE19843423181 priority Critical patent/DE3423181A1/de
Priority to EP85107263A priority patent/EP0167867A3/de
Priority to IL75551A priority patent/IL75551A0/xx
Priority to DK278185A priority patent/DK278185A/da
Priority to DD85277577A priority patent/DD234643A5/de
Priority to KR1019850004389A priority patent/KR860000711A/ko
Priority to GR851516A priority patent/GR851516B/el
Priority to ZA854662A priority patent/ZA854662B/xx
Priority to FI852464A priority patent/FI852464L/fi
Priority to BR8502956A priority patent/BR8502956A/pt
Priority to NO852512A priority patent/NO852512L/no
Priority to ES544405A priority patent/ES8701453A1/es
Priority to PT80686A priority patent/PT80686B/pt
Priority to CA000484824A priority patent/CA1224884A/en
Priority to PL25411885A priority patent/PL254118A1/xx
Priority to JP60134463A priority patent/JPS6169197A/ja
Priority to AU43951/85A priority patent/AU4395185A/en
Priority to HU852453A priority patent/HUT39311A/hu
Publication of DE3423181A1 publication Critical patent/DE3423181A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/47—Organic layers, e.g. photoresist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10598—Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Details Of Indoor Wiring (AREA)
DE19843423181 1984-06-22 1984-06-22 Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten Withdrawn DE3423181A1 (de)

Priority Applications (18)

Application Number Priority Date Filing Date Title
DE19843423181 DE3423181A1 (de) 1984-06-22 1984-06-22 Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten
EP85107263A EP0167867A3 (de) 1984-06-22 1985-06-12 Fixierter Lagenaufbau und Verfahren zur Herstellung von Mehrlagenleiterplatten unter Verwendung dieses Lagenaufbaus
IL75551A IL75551A0 (en) 1984-06-22 1985-06-18 Method of producing multilayer circuit boards,a fixed layered structure produced by this method,and the use of this layered structure in this production method
DK278185A DK278185A (da) 1984-06-22 1985-06-19 Fremgangsmaade til fremstilling af trykte kredsloebskort med flere lag, fikseret opbygning af lag ifoelge fremgangsmaaden og anvendelse af opbygningen af lag ved fremstillingsfremgangsmaaden
DD85277577A DD234643A5 (de) 1984-06-22 1985-06-20 Verfahren zur herstellung von mehrlagenleiterplatten, nach diesem verfahren hergestellter, fixierter lagenaufbau und verwendung dieses lagenaufbaus bei diesem herstellungsverfahren
KR1019850004389A KR860000711A (ko) 1984-06-22 1985-06-20 다층회로 기판과 그 제조방법
GR851516A GR851516B (enEXAMPLES) 1984-06-22 1985-06-20
ZA854662A ZA854662B (en) 1984-06-22 1985-06-20 Multi-layer circuit boards
FI852464A FI852464L (fi) 1984-06-22 1985-06-20 Foerfarande foer framstaellning av flerskiktkretskort en medelst detta foerfarande framstaelld, fastsatt skiktstruktur och anvaendning av denna skiktstruktur i detta framstaellningsfoerfarande.
BR8502956A BR8502956A (pt) 1984-06-22 1985-06-20 Processo e estruturacao das camadas para a fabricacao de multiplacas de circuito impresso,e uso da estruturacao prefixada de camadas
NO852512A NO852512L (no) 1984-06-22 1985-06-21 Fremgangsmaate og anordning for fremstilling av flerlagslederplater.
ES544405A ES8701453A1 (es) 1984-06-22 1985-06-21 Procedimiento para la fabricacion de placas de circuito impreso de capas multiples.
PT80686A PT80686B (de) 1984-06-22 1985-06-21 Verfahren zur herstellung von mehrlagenleiterplatten nach diesem verfahren hergestellter fixierter langenaufbaus bei diesen herstellungsverfahren
CA000484824A CA1224884A (en) 1984-06-22 1985-06-21 Method of producing multilayer circuit boards, a fixed layered structure produced by this method, and the use of this layered structure in this production method
PL25411885A PL254118A1 (en) 1984-06-22 1985-06-21 Method of manufacturing multilayer printed boards and layer arrangement in printed boards made using this method
JP60134463A JPS6169197A (ja) 1984-06-22 1985-06-21 多層印刷回路板を製造する方法および層構造
AU43951/85A AU4395185A (en) 1984-06-22 1985-06-21 Producing multilayer circuit boards
HU852453A HUT39311A (en) 1984-06-22 1985-06-21 Method for laying out multilayer printed circuit structure, multilayer structure laid out thereby and the use thereof for making multilayer printed circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843423181 DE3423181A1 (de) 1984-06-22 1984-06-22 Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten

Publications (1)

Publication Number Publication Date
DE3423181A1 true DE3423181A1 (de) 1986-01-02

Family

ID=6238964

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843423181 Withdrawn DE3423181A1 (de) 1984-06-22 1984-06-22 Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten

Country Status (18)

Country Link
EP (1) EP0167867A3 (enEXAMPLES)
JP (1) JPS6169197A (enEXAMPLES)
KR (1) KR860000711A (enEXAMPLES)
AU (1) AU4395185A (enEXAMPLES)
BR (1) BR8502956A (enEXAMPLES)
CA (1) CA1224884A (enEXAMPLES)
DD (1) DD234643A5 (enEXAMPLES)
DE (1) DE3423181A1 (enEXAMPLES)
DK (1) DK278185A (enEXAMPLES)
ES (1) ES8701453A1 (enEXAMPLES)
FI (1) FI852464L (enEXAMPLES)
GR (1) GR851516B (enEXAMPLES)
HU (1) HUT39311A (enEXAMPLES)
IL (1) IL75551A0 (enEXAMPLES)
NO (1) NO852512L (enEXAMPLES)
PL (1) PL254118A1 (enEXAMPLES)
PT (1) PT80686B (enEXAMPLES)
ZA (1) ZA854662B (enEXAMPLES)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991018491A1 (en) * 1990-05-16 1991-11-28 Perstorp Ab Process for the production of a multilayer printed circuit board
US5832596A (en) * 1996-12-31 1998-11-10 Stmicroelectronics, Inc. Method of making multiple-bond shelf plastic package

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1261481A (en) * 1986-03-13 1989-09-26 Kazumasa Eguchi Printed circuit board capable of preventing electromagnetic interference
JPS62295488A (ja) * 1986-06-14 1987-12-22 松下電工株式会社 多層プリント配線板の製法
DE3819785A1 (de) * 1988-06-10 1989-12-14 Ferrozell Sachs & Co Gmbh Verfahren zum herstellen von mehrlagigen, gedruckten leiterplatten
CH678412A5 (enEXAMPLES) * 1988-11-11 1991-09-13 Fela Planungs Ag

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196598A (en) * 1981-05-29 1982-12-02 Hitachi Ltd Method of producing multilayer printed board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991018491A1 (en) * 1990-05-16 1991-11-28 Perstorp Ab Process for the production of a multilayer printed circuit board
US5336353A (en) * 1990-05-16 1994-08-09 Polyclad Europe Ab Process for the production of a multilayer printed circuit board
US5832596A (en) * 1996-12-31 1998-11-10 Stmicroelectronics, Inc. Method of making multiple-bond shelf plastic package

Also Published As

Publication number Publication date
IL75551A0 (en) 1985-10-31
DK278185A (da) 1985-12-23
EP0167867A2 (de) 1986-01-15
FI852464A7 (fi) 1985-12-23
AU4395185A (en) 1986-01-02
NO852512L (no) 1985-12-23
ES544405A0 (es) 1986-11-16
FI852464L (fi) 1985-12-23
KR860000711A (ko) 1986-01-30
GR851516B (enEXAMPLES) 1985-11-25
HUT39311A (en) 1986-08-28
FI852464A0 (fi) 1985-06-20
EP0167867A3 (de) 1987-01-28
ES8701453A1 (es) 1986-11-16
PL254118A1 (en) 1986-05-06
DK278185D0 (da) 1985-06-19
ZA854662B (en) 1986-04-30
PT80686B (de) 1987-02-12
JPS6169197A (ja) 1986-04-09
PT80686A (de) 1985-07-01
CA1224884A (en) 1987-07-28
DD234643A5 (de) 1986-04-09
BR8502956A (pt) 1986-03-04

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Legal Events

Date Code Title Description
8127 New person/name/address of the applicant

Owner name: PRESIDENT ENGINEERING CORP., ZUERICH, CH

8128 New person/name/address of the agent

Representative=s name: BERG, W., DIPL.-CHEM. DR.RER.NAT., PAT.-ANW., 8000

8128 New person/name/address of the agent

Representative=s name: SCHWABE, H., DIPL.-ING. SANDMAIR, K., DIPL.-CHEM.

8128 New person/name/address of the agent

Representative=s name: BLUMBACH, P., DIPL.-ING., 6200 WIESBADEN WESER, W.

8139 Disposal/non-payment of the annual fee