FI852464A0 - Foerfarande foer framstaellning av flerskiktkretskort en medelst detta foerfarande framstaelld, fastsatt skiktstruktur och anvaendning av denna skiktstruktur i detta framstaellningsfoerfarande. - Google Patents

Foerfarande foer framstaellning av flerskiktkretskort en medelst detta foerfarande framstaelld, fastsatt skiktstruktur och anvaendning av denna skiktstruktur i detta framstaellningsfoerfarande.

Info

Publication number
FI852464A0
FI852464A0 FI852464A FI852464A FI852464A0 FI 852464 A0 FI852464 A0 FI 852464A0 FI 852464 A FI852464 A FI 852464A FI 852464 A FI852464 A FI 852464A FI 852464 A0 FI852464 A0 FI 852464A0
Authority
FI
Finland
Prior art keywords
skiktstruktur
detta
foerfarande
flerskiktkretskort
fastsatt
Prior art date
Application number
FI852464A
Other languages
English (en)
Other versions
FI852464L (fi
Inventor
Rainer Burger
Original Assignee
President Eng Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by President Eng Corp filed Critical President Eng Corp
Publication of FI852464A0 publication Critical patent/FI852464A0/fi
Publication of FI852464L publication Critical patent/FI852464L/fi

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/47Organic layers, e.g. photoresist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10598Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Details Of Indoor Wiring (AREA)
FI852464A 1984-06-22 1985-06-20 Foerfarande foer framstaellning av flerskiktkretskort en medelst detta foerfarande framstaelld, fastsatt skiktstruktur och anvaendning av denna skiktstruktur i detta framstaellningsfoerfarande. FI852464L (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843423181 DE3423181A1 (de) 1984-06-22 1984-06-22 Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten

Publications (2)

Publication Number Publication Date
FI852464A0 true FI852464A0 (fi) 1985-06-20
FI852464L FI852464L (fi) 1985-12-23

Family

ID=6238964

Family Applications (1)

Application Number Title Priority Date Filing Date
FI852464A FI852464L (fi) 1984-06-22 1985-06-20 Foerfarande foer framstaellning av flerskiktkretskort en medelst detta foerfarande framstaelld, fastsatt skiktstruktur och anvaendning av denna skiktstruktur i detta framstaellningsfoerfarande.

Country Status (18)

Country Link
EP (1) EP0167867A3 (fi)
JP (1) JPS6169197A (fi)
KR (1) KR860000711A (fi)
AU (1) AU4395185A (fi)
BR (1) BR8502956A (fi)
CA (1) CA1224884A (fi)
DD (1) DD234643A5 (fi)
DE (1) DE3423181A1 (fi)
DK (1) DK278185A (fi)
ES (1) ES8701453A1 (fi)
FI (1) FI852464L (fi)
GR (1) GR851516B (fi)
HU (1) HUT39311A (fi)
IL (1) IL75551A0 (fi)
NO (1) NO852512L (fi)
PL (1) PL254118A1 (fi)
PT (1) PT80686B (fi)
ZA (1) ZA854662B (fi)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801489A (en) * 1986-03-13 1989-01-31 Nintendo Co., Ltd. Printed circuit board capable of preventing electromagnetic interference
JPS62295488A (ja) * 1986-06-14 1987-12-22 松下電工株式会社 多層プリント配線板の製法
DE3819785A1 (de) * 1988-06-10 1989-12-14 Ferrozell Sachs & Co Gmbh Verfahren zum herstellen von mehrlagigen, gedruckten leiterplatten
CH678412A5 (fi) * 1988-11-11 1991-09-13 Fela Planungs Ag
SE9001766L (sv) * 1990-05-16 1991-09-02 Perstorp Ab Saett vid tillverkning av flerlagermoensterkort
US5832596A (en) * 1996-12-31 1998-11-10 Stmicroelectronics, Inc. Method of making multiple-bond shelf plastic package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196598A (en) * 1981-05-29 1982-12-02 Hitachi Ltd Method of producing multilayer printed board

Also Published As

Publication number Publication date
AU4395185A (en) 1986-01-02
KR860000711A (ko) 1986-01-30
ES544405A0 (es) 1986-11-16
BR8502956A (pt) 1986-03-04
CA1224884A (en) 1987-07-28
ES8701453A1 (es) 1986-11-16
EP0167867A2 (de) 1986-01-15
HUT39311A (en) 1986-08-28
EP0167867A3 (de) 1987-01-28
IL75551A0 (en) 1985-10-31
DD234643A5 (de) 1986-04-09
ZA854662B (en) 1986-04-30
DE3423181A1 (de) 1986-01-02
JPS6169197A (ja) 1986-04-09
PT80686B (de) 1987-02-12
DK278185A (da) 1985-12-23
PL254118A1 (en) 1986-05-06
GR851516B (fi) 1985-11-25
PT80686A (de) 1985-07-01
DK278185D0 (da) 1985-06-19
NO852512L (no) 1985-12-23
FI852464L (fi) 1985-12-23

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Legal Events

Date Code Title Description
FA Application withdrawn

Owner name: PRESIDENT ENGINEERING CORP.