DE3382251D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3382251D1
DE3382251D1 DE8383102836T DE3382251T DE3382251D1 DE 3382251 D1 DE3382251 D1 DE 3382251D1 DE 8383102836 T DE8383102836 T DE 8383102836T DE 3382251 T DE3382251 T DE 3382251T DE 3382251 D1 DE3382251 D1 DE 3382251D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory
decoder
memory arrangement
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383102836T
Other languages
English (en)
Inventor
Hiroshi Iwahashi
Shoji Ariizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57047724A external-priority patent/JPS58164100A/ja
Priority claimed from JP57047722A external-priority patent/JPS58164098A/ja
Priority claimed from JP57056278A external-priority patent/JPS58175196A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3382251D1 publication Critical patent/DE3382251D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
DE8383102836T 1982-03-25 1983-03-22 Halbleiterspeicheranordnung. Expired - Lifetime DE3382251D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP57047724A JPS58164100A (ja) 1982-03-25 1982-03-25 半導体メモリ−
JP57047722A JPS58164098A (ja) 1982-03-25 1982-03-25 半導体メモリ−
JP57056278A JPS58175196A (ja) 1982-04-05 1982-04-05 半導体メモリ−

Publications (1)

Publication Number Publication Date
DE3382251D1 true DE3382251D1 (de) 1991-05-23

Family

ID=27293059

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383102836T Expired - Lifetime DE3382251D1 (de) 1982-03-25 1983-03-22 Halbleiterspeicheranordnung.

Country Status (3)

Country Link
US (1) US4571706A (de)
EP (1) EP0090331B1 (de)
DE (1) DE3382251D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4729119A (en) * 1984-05-21 1988-03-01 General Computer Corporation Apparatus and methods for processing data through a random access memory system
JPS6148200A (ja) * 1984-08-14 1986-03-08 Fujitsu Ltd 半導体記憶装置
FR2613524A1 (fr) * 1987-04-03 1988-10-07 Thomson Csf Procede a acces aleatoire a zone de reparation et procede de reparation d'une telle memoire
JPH01224999A (ja) * 1988-03-04 1989-09-07 Mitsubishi Electric Corp 半導体記憶装置
JP2837433B2 (ja) * 1989-06-05 1998-12-16 三菱電機株式会社 半導体記憶装置における不良ビット救済回路
US5471427A (en) * 1989-06-05 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Circuit for repairing defective bit in semiconductor memory device and repairing method
JP2784550B2 (ja) * 1990-03-05 1998-08-06 三菱電機株式会社 半導体記憶装置
JP2980472B2 (ja) * 1992-12-21 1999-11-22 株式会社東芝 半導体記憶装置
US6526470B1 (en) * 1998-09-28 2003-02-25 Cypress Semiconductor Corp. Fifo bus-sizing, bus-matching datapath architecture
KR100684896B1 (ko) * 2005-04-20 2007-02-20 삼성전자주식회사 반도체 메모리 장치의 출력버퍼회로
CN102385533A (zh) * 2010-08-30 2012-03-21 鸿富锦精密工业（深圳）有限公司 计算机及其内存运行错误时的重启方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1963895C3 (de) * 1969-06-21 1973-11-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Datenspeicher und Datenspeicher anste'uerschaltung
US3940740A (en) * 1973-06-27 1976-02-24 Actron Industries, Inc. Method for providing reconfigurable microelectronic circuit devices and products produced thereby
JPS5685934A (en) * 1979-12-14 1981-07-13 Nippon Telegr & Teleph Corp <Ntt> Control signal generating circuit
US4281398A (en) * 1980-02-12 1981-07-28 Mostek Corporation Block redundancy for memory array

Also Published As

Publication number Publication date
EP0090331A3 (en) 1987-03-18
EP0090331A2 (de) 1983-10-05
EP0090331B1 (de) 1991-04-17
US4571706A (en) 1986-02-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee