DE3381476D1 - Pufferspeichersteuerungsanordnung. - Google Patents

Pufferspeichersteuerungsanordnung.

Info

Publication number
DE3381476D1
DE3381476D1 DE8383107561T DE3381476T DE3381476D1 DE 3381476 D1 DE3381476 D1 DE 3381476D1 DE 8383107561 T DE8383107561 T DE 8383107561T DE 3381476 T DE3381476 T DE 3381476T DE 3381476 D1 DE3381476 D1 DE 3381476D1
Authority
DE
Germany
Prior art keywords
buffer memory
memory control
control arrangement
arrangement
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383107561T
Other languages
English (en)
Inventor
Kanji Kubo
Kenichi Wada
Yooichi Shintani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3381476D1 publication Critical patent/DE3381476D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE8383107561T 1982-09-10 1983-08-01 Pufferspeichersteuerungsanordnung. Expired - Lifetime DE3381476D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57156634A JPS5948879A (ja) 1982-09-10 1982-09-10 記憶制御方式

Publications (1)

Publication Number Publication Date
DE3381476D1 true DE3381476D1 (de) 1990-05-23

Family

ID=15631956

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383107561T Expired - Lifetime DE3381476D1 (de) 1982-09-10 1983-08-01 Pufferspeichersteuerungsanordnung.

Country Status (4)

Country Link
US (1) US4618926A (de)
EP (1) EP0103132B1 (de)
JP (1) JPS5948879A (de)
DE (1) DE3381476D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60181942A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd メモリ制御装置
JPS6126151A (ja) * 1984-07-17 1986-02-05 Fujitsu Ltd バツフア制御方式
US4774653A (en) * 1985-08-07 1988-09-27 Hewlett-Packard Company Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
US4868737A (en) * 1986-12-22 1989-09-19 Tandberg Data A/S Method and arrangement in which capacity of a related storage medium is checked when buffering data
JP2561261B2 (ja) * 1987-02-18 1996-12-04 株式会社日立製作所 バッファ記憶アクセス方法
JPS63257853A (ja) * 1987-04-03 1988-10-25 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン キヤツシユ・メモリ・システム
JPH0769819B2 (ja) * 1987-09-28 1995-07-31 日本電気株式会社 情報処理装置
KR920001282B1 (ko) * 1987-10-02 1992-02-10 가부시키가이샤 히타치세이사쿠쇼 버퍼메모리 제어장치
IT1216086B (it) * 1988-03-15 1990-02-22 Honeywell Bull Spa Memoria tampone ad indirizzamento pseudo virtuale.
JPH0774994B2 (ja) * 1988-09-21 1995-08-09 株式会社日立製作所 バッファ記憶制御装置のｏｓｃ検出方式
JPH0748191B2 (ja) * 1989-08-10 1995-05-24 株式会社日立製作所 バッファ記憶制御装置
JPH03216744A (ja) * 1990-01-22 1991-09-24 Fujitsu Ltd 内蔵キャッシュ・メモリ制御方式
US5235697A (en) * 1990-06-29 1993-08-10 Digital Equipment Set prediction cache memory system using bits of the main memory address
US5555389A (en) * 1993-07-07 1996-09-10 Hitachi, Ltd. Storage controller for performing dump processing

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829840A (en) * 1972-07-24 1974-08-13 Ibm Virtual memory system
JPS5440182B2 (de) * 1974-02-26 1979-12-01
GB1472885A (en) * 1974-05-01 1977-05-11 Int Computers Ltd Digital code conversion arrangements
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
US4070706A (en) * 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system
US4149242A (en) * 1977-05-06 1979-04-10 Bell Telephone Laboratories, Incorporated Data interface apparatus for multiple sequential processors
US4339804A (en) * 1979-07-05 1982-07-13 Ncr Corporation Memory system wherein individual bits may be updated
US4471429A (en) * 1979-12-14 1984-09-11 Honeywell Information Systems, Inc. Apparatus for cache clearing
JPS5687282A (en) * 1979-12-14 1981-07-15 Nec Corp Data processor
US4493033A (en) * 1980-04-25 1985-01-08 Data General Corporation Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
US4467414A (en) * 1980-08-22 1984-08-21 Nippon Electric Co., Ltd. Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4424561A (en) * 1980-12-31 1984-01-03 Honeywell Information Systems Inc. Odd/even bank structure for a cache memory
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache

Also Published As

Publication number Publication date
EP0103132B1 (de) 1990-04-18
JPS6153746B2 (de) 1986-11-19
EP0103132A2 (de) 1984-03-21
EP0103132A3 (en) 1987-04-08
US4618926A (en) 1986-10-21
JPS5948879A (ja) 1984-03-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition